2 Replies Latest reply on Oct 5, 2020 6:27 AM by KyWe_1936431

    peripheral clock for DMA sine wave fll clock vs. imo



      I previously asked about the internal main oscillator clock (IMO) not allowing the maximum sine wave frequency when using the sample project (https://www.cypress.com/documentation/code-examples/ce220924-psoc-6-mcu-vdac-sine-wave-generator-using-dma ) and figured out if I use the FLL as the clock source for the peripheral clock I can achieve a higher frequency. PSoC 6 MCU VDAC Sine Wave Generator Using DMA using CYBLE-416045-EVAL EZ-BLE cannot achieve 5kHz sine wave


      As stated there I get the following following frequencies of the sine wave using the IMO as the source


      d is the divider, and f is the frequency of the sine in kHz, ef is expected frequency

      d=16      f=3.16      ef=5

      d=17      f=3.58      ef=4.7

      d=18      f=4.24      ef=4.4

      d=19      f=4.0        ef=4.2


      I would like to know why the IMO can't produce the expected frequencies when using the lowest dividers.


      Thank you,