peripheral clock for DMA sine wave fll clock vs. imo

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KyWe_1936431
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Hello,

I previously asked about the internal main oscillator clock (IMO) not allowing the maximum sine wave frequency when using the sample project (https://www.cypress.com/documentation/code-examples/ce220924-psoc-6-mcu-vdac-sine-wave-generator-usi... ) and figured out if I use the FLL as the clock source for the peripheral clock I can achieve a higher frequency. PSoC 6 MCU VDAC Sine Wave Generator Using DMA using CYBLE-416045-EVAL EZ-BLE cannot achieve 5kHz sin...

As stated there I get the following following frequencies of the sine wave using the IMO as the source

d is the divider, and f is the frequency of the sine in kHz, ef is expected frequency

d=16      f=3.16      ef=5

d=17      f=3.58      ef=4.7

d=18      f=4.24      ef=4.4

d=19      f=4.0        ef=4.2

I would like to know why the IMO can't produce the expected frequencies when using the lowest dividers.

Thank you,

Kyle

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3 Replies
Vasanth
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250 sign-ins 500 solutions authored First question asked

Hi Kyle,


I will try to recreate the issue. Kindly confirm the use case. Code Example: CE220924, PSoC Creator 4.3

You are keeping the Peripheral clock as 8MHz and setting the divider for the clock source. Your observations on sine wave frequency with respect to divider value is provided. Kindly confirm

Best Regards,
Vasanth

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Hi Vasanth,

Yes that is the code example and creator version. I did use the CYBLE-416045-EVAL EZ-BLE board and I changed the power mode to .9V SIMO buck, and the debug select to GPIO. Yes peripheral clock is 8MHz and the list I provided is sine wave frequency with respect to Divider values. I did end up using the fractional divider with the same or similar results. let me know if you want me to attach the project.

Thanks and good luck,

Kyle

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Vasanth
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250 sign-ins 500 solutions authored First question asked

Hello Kyle,

Apologies for the late update. The clock divider is working as expected in your case. You can connect a pin on the output trigger of the CTDAC and see periodic output triggers corresponding to clock input on it. The problem as I understand is from the DMA side of the things, where the DMA clock (clock_slow) also got reduced with the change in the peripheral clock value. Enabling DMA trigger out and connecting a pin at the output we can see the resulting trigger out after each transfer, causing the waveform with a different frequency than expected.

Best Regards,
Vasanth

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