3 Replies Latest reply on Oct 10, 2020 8:04 PM by WaHo_4359701

    S25FL512SAGBAEA10 Timing with Write enable Command and Page Program command

    DaNe_4783256

      Hello,

       

      I am using S25FL512SAGBAEA10 SPI flash and I have a question based on the timing with the write enable command (06h) and the page program (02h). Essentially I am wondering how long do I have to wait before sending a page program command after sending the write enable command. I just want to write a file to the SPI flash.

       

      The datasheet says "CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. Without CS# being driven to the logic high state after the eighth bit of the instruction byte has been latched in on SI, the write enable operation will not be executed". This statement I feel is true but doesnt tell you everything you need to know. I have tried to follow this with a page program command immediately after sending a write enable command and it has not worked even when I have comfirmed that the CS# goes back high in between with a 20 ns delay in between. Is there some delay I need to have in between the commands so that the write enable actually executes? Is it based off SCK? I'm trying to find this in your datasheet but I'm failing to find it. I'm using Document Number 001-98284 Rev *Q.

       

      Note: I can set the write enable bit but theres some timing relationship between commands that must be getting violated.

       

      In the meantime I am going to try a 100 ns second delay to see if that fixes things and try to re-read the datasheet and try to get the simulation model for the SPI flash working.

       

      Thanks, Dan