Pre-load simulation model for S29GL512S12DHE010 to an erased condition

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DaNe_4783256
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Level 1
First solution authored

Hello,

I was hoping to load default values into the memory array, CFI field and protection bits for the S29GL512S12DHE010 for the VHDL simuation model for the S29GL512S. How do I do this? The user manual leaves a lot to be desired and I dont know how to do it. It would be great if one could be created for me. It looks like if I make the UserPreload false, it defaults everything to undefined (U) and I would think that would force me to issue an erase command then send a write command. The test bench calls out these files as constants but I dont see where these files are at all for a different flash part. All I want to do is send write to buffer, and word program commands. I may also want to read commands so having a template of sort that I can modify would be a great help. Unfortunally the provided simulation model to my knowledge doesn't address this at least in a clear, easy to understand way. Essentially I want my simulation to have FFFF written everywhere to start.

Thanks, Dan

Note: I asked this in the Community information topic area by mistake.

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Hello Daniel

Attach is a complete run dir including pre-load files that can serve as an example.

The code is executing in QuestaSim. You can use that as is:

vsim -sdftyp s29gl512s_vhdl.sdf testbench_s29gl512s_vhdl

run -all

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DaNe_4783256
Level 1
Level 1
First solution authored

....Trying to get the simulation model working because there doesnt seem to be information on a buffer to write waveform in the datasheet. Figure 11.14 in the datasheet goes into a page program but not a buffer to write command sequence. When I write a large file every place is going to 0000 instead of non-zero values like how my FPGA is driving it as I can tell using a debugger. Either I'm doing it wrong the write to buffer command sequence wrong with the read/busy signal, or I have a failure in the flash or some hardware issue. Right now I'm thinking its something to do with VHDL source code. The datasheet really should have a write to buffer waveform to show the differences and be more clear.

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lock attach
Attachments are accessible only for community members.

Hello Daniel

Attach is a complete run dir including pre-load files that can serve as an example.

The code is executing in QuestaSim. You can use that as is:

vsim -sdftyp s29gl512s_vhdl.sdf testbench_s29gl512s_vhdl

run -all

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