3 Replies Latest reply on Sep 24, 2020 10:11 AM by AnCo_4758931

    FX3 terminology question:  What is the "P" in "P-Port"?


      I know this is a bit silly but understanding abbreviations is important to me, especially if I'm expected to use (and thus document) them in my own source code.  I understand that the "P-Port" or just "PP" refers to the GPIF II interface (and is abbreviated further to just "P" in "U2P" and "P2U" descriptions of DMA channels), but I haven't found any documentation that explains what that initial P stands for.  Parallel?  Peripheral?  Processor?  Something else?  It would be nice to have an official definition for this abbreviation included in the documentation.  If it already exists somewhere please point me to it.

        • 1. Re: FX3 terminology question:  What is the "P" in "P-Port"?



          The "P" in "P-Port" refers to Processor. Please refer to section 4.2 in Page 4 of AN75705 which mentions this. The link to the Application note is given below:



          Best Regards,


          • 2. Re: FX3 terminology question:  What is the "P" in "P-Port"?

            I'm sorry but I don't see that anywhere in section 4.2 of AN75705.  At best it defines GPIF II as part of the PIB, but makes no mention of P-Port.  Did you link the correct AppNote?


            4.2 GPIF II

            The high-performance GPIF II (a part of the processor interface block (PIB)) enables functionality similar to, but more

            advanced than, FX2LP's GPIF and Slave FIFO interfaces. GPIF II is a programmable state machine that enables a

            flexible interface running on its own high-speed clock, autonomous to the Arm9. GPIF II may either function as a master

            or slave in industry-standard or proprietary interfaces. Both parallel and serial interfaces may be implemented with

            GPIF II.

            The key features of GPIF II are:

            ▪ Functions as master or slave.

            ▪ Provides 256 programmable states.

            ▪ Supports 8-bit, 16-bit, 24-bit, and 32-bit parallel data bus.

            ▪ Supports interface frequencies up to 100 MHz.

            ▪ Supports 14 configurable I/O pins (to function as control signals) when a 32- bit data bus is used. Control pins can

            be input, output, or bidirectional.

            ▪ Supports 16 control I/O pins when a 16/8 data bus is used. Control pins can be input, output, or bi-directional.

            Cypress’s GPIF II Designer Tool enables fast development of GPIF II state machines and includes examples for

            common interfaces. The GPIF II Designer Tool is available with the EZ-USB FX3 SDK installation.

            A popular implementation of GPIF II is a synchronous Slave FIFO interface, used in many FPGA interfaces. For details

            on the synchronous Slave FIFO interface, refer to AN65974 - Designing with the EZ-USB FX3 Slave FIFO Interface.

            • 3. Re: FX3 terminology question:  What is the "P" in "P-Port"?

              While I don't see it in the app note you linked, I checked further and do see your answer verified in the document "EZ-USB FX3 Firmware Library API Reference Guide Version 1.3.4" in section (describing CyU3PDeviceConfigureIOMatrix):


              The processor port (P-port) of the device can be configured as a GPIF interface.


              Based on that I'll flag your answer as correct.  Thanks!