3 Replies Latest reply on Sep 24, 2020 6:35 AM by RakshithM_16

    CySysFlashWriteRow(...) while UART TX (2nd)

    MaPe_1936286

      Hello,

      this is a prosecution of my previous question: CySysFlashWriteRow(...) while UART TX

      The problem regards the UART transmission while the Flash is writing a row, by using a "CY8CKIT-149 PSoC 4100S Plus Prototyping Kit".

      The problem was solved by correcting the IMO to 48MHz.

       

      When the IMO is set to 48MHz also the HFClk change to 48MHz, but I need to keep the HFClk at 24 MHz and so I changed its divider to 2.

      Now, with IMO=48MHz and HFClk=24MHz I still have the transmission problem while the Flash is writing a row, even if IMO is 48MHz.

        • 1. Re: CySysFlashWriteRow(...) while UART TX (2nd)
          GaneshD_41

          Hi,

           

          "The problem was solved by correcting the IMO to 48MHz."

          "Now, with IMO=48MHz and HFClk=24MHz I still have the transmission problem while the Flash is writing a row, even if IMO is 48MHz."

           

          I have tested the attached project and found that when I press the character 'r' the following output is getting in the teraterm.

          Can you please tell us what is the new problem you are facing? and the steps to reproduce the issue?

           

          print.PNG

           

          Thanks

          Ganesh

           

           

          • 2. Re: CySysFlashWriteRow(...) while UART TX (2nd)
            MaPe_1936286

            Hi Ganesh,

            this is the wrong output I get when the divider is equal to 2:

            Divider_2.jpg

            And if I change the divider to 1 the output I get is correct:

            Divider_1.jpg

            I also replaced my CY8KIT-149 with another one but the output is the same.

             

            Thanks

            Maurizio

            • 3. Re: CySysFlashWriteRow(...) while UART TX (2nd)
              RakshithM_16

              Hi MaPe_1936286,

               

              Flash writes automatically modify the IMO and the HF clocks as mentioned in the documentation, which is why the UART block is affected which derives its clock automatically from HF Clock.

              The variations in the HF Clock frequency might be below the UART tolerance and that might be the reason why it is working when the clock divider is set to 1. The same is observed with different baud rates as well. For further details regarding the UART clock frequency and tolerance, please refer to the component datasheet.

               

              Hope this helps,

               

              Thanks and Regards,

              Rakshith M B

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