6 Replies Latest reply on Oct 15, 2020 8:00 PM by HaJi_4128141

    PSoC5lp External Clock voltage level, DelSig 1.2V reference, Vddio Vdda voltage relationship, decoupling capacitor values

    HaJi_4128141

      Hello there,

       

      I am trying to design my own PSoC5lp board, and are having some confusions amont some points.

       

      1. According to the "PSoC® 3 and PSoC 5LP External Oscillator - AN54439", I am able to attach an external oscillator (like TXCO) to the XtalIn so that the clock would route from MHzECO to the clock tree. If I power the PSoC5lp using 5V at Vdda and Vddd, could I use an 3.3V output TXCO? Or more of how many volt in terms of "high level" does XtalIn require to operate correctly?

       

      2. From TRM, I see there exist an 1.2V voltage reference for DelSig. Is there a way to access it?

       

      3. If I power the PSoC5lp's Vdda at 5V, but for a specific Vddiox I do 3.3v, and if I use a pin under this 3.3V Vddiox section as analog input/output, could the voltage at this pin higher than 3.3v? Let say can I output 4V from a DAC out from a pin under a 3.3V Vddiox?

       

      4.  "PSoC 3 and PSoC 5LP Hardware Design Considerations" suggests 0.1u and 1u capacitors for decoupling purposes, but from power supply impedance perspective (PDN analysis), we know that combination of those two values normally would not give us a good low impedance power supply input impedance across all frequencies. Is that ok if I do capacitors from 10n 100n 1u 20u in parallel for all of those supplies pins for a very strict EMC design? Does Cypress suggest 0.1u and 1u due to internal LDO's stability constrains?

       

      If anyone can help me out from those questions I would really appreciated.

       

      Thanks a lot!

       

      Hanpeng

        • 1. Re: PSoC5lp External Clock voltage level, DelSig 1.2V reference, Vddio Vdda voltage relationship, decoupling capacitor values
          GaneshD_41

          Hi Hanpeng,

           

          2. From TRM, I see there exist an 1.2V voltage reference for DelSig. Is there a way to access it?

           

          You can get the 1.024 volts reference as a component in PSoC Creator schematic page. You can drag and drop it into your schematic page.

           

          3. If I power the PSoC5lp's Vdda at 5V, but for a specific Vddiox I do 3.3v, and if I use a pin under this 3.3V Vddiox section as analog input/output, could the voltage at this pin higher than 3.3v? Let say can I output 4V from a DAC out from a pin under a 3.3V Vddiox?

           

          Please refer Table 11-1. Absolute Maximum Ratings DC Specifications from the PSoC 5LP device datasheet. It says the maximum voltage on the GPIO pin should not exceed VDDIO + 0.5 volts. Maximum voltage on GPIO pin ≤ VDDIO ≤ VDDA.

          Datasheet: https://www.cypress.com/file/45906/download

          Please refer GPO cell architecture from Section 19. I/O system (page number 140) from PSoC 5LP architecture TRM to understand more about this constraint.

          Architecture TRM: https://www.cypress.com/file/123561/download

           

          4.  "PSoC 3 and PSoC 5LP Hardware Design Considerations" suggests 0.1u and 1u capacitors for decoupling purposes, but from power supply impedance perspective (PDN analysis), we know that combination of those two values normally would not give us a good low impedance power supply input impedance across all frequencies. Is that ok if I do capacitors from 10n 100n 1u 20u in parallel for all of those supplies pins for a very strict EMC design? Does Cypress suggest 0.1u and 1u due to internal LDO's stability constrains?

           

          Yes. You can add more capacitors. The values mentioned in appnote are basic Cypress recommendations which may not solve complex EMC problems.

          Please note that you need to keep the 0.1uF capacitor with in 1cn from the pin. This is the only strict recommendation.

           

          Hope this helps !

           

          Thanks

          Ganesh

           

          • 2. Re: PSoC5lp External Clock voltage level, DelSig 1.2V reference, Vddio Vdda voltage relationship, decoupling capacitor values
            HaJi_4128141

            Dear Ganesh,

             

            Thank you very much for your reply!

             

            For question 2, do you mean that the 1.2V reference is inaccessible? Only the 1.024V one is accessible?

             

            For question 3, sorry I forgot about the maximum rating table. Just a note that I also realized it from the I/O circuit diagram, where there are ESD protection diode connecting from pin to Vddiox.

             

            I would like to ask will there be any info about the question 1 (the external clock one)? Since it indeed quite important for my design...

             

            And an extra question, can I also connect a TXCO to the kHzECO pin using the same way as the MHzECO?

             

            Thanks again!

            Hanpeng

            • 3. Re: PSoC5lp External Clock voltage level, DelSig 1.2V reference, Vddio Vdda voltage relationship, decoupling capacitor values
              EktaN_26

              Hi Hanpeng,

               

              For 1. According to the "PSoC® 3 and PSoC 5LP External Oscillator - AN54439", I am able to attach an external oscillator (like TXCO) to the XtalIn so that the clock would route from MHzECO to the clock tree. If I power the PSoC5lp using 5V at Vdda and Vddd, could I use an 3.3V output TXCO? Or more of how many volt in terms of "high level" does XtalIn require to operate correctly?

               

              Please refer to the datasheet Table 8-11 in case of GPIO pins and Table 11-10 in case of SIO pins (page 76 and page 78). The VIH  parameter signifies the voltage required at the pin to detect a high (Input voltage high threshold). For example in case of GPIO pins it is 0.7*VDDIO which is 3.5V in your case.

               

              And an extra question, can I also connect a TXCO to the kHzECO pin using the same way as the MHzECO?

               

              Please refer to the CY8CKIT-050 Development Kit Guide (page 42) which shows how the kHz crystal was connected  in case of the kit. You can connect the kHz ECO in the same way.

               

              Best Regards

              Ekta

              • 5. Re: PSoC5lp External Clock voltage level, DelSig 1.2V reference, Vddio Vdda voltage relationship, decoupling capacitor values
                BoTa_264741

                Haji,

                >Is that ok if I do capacitors from 10n 100n 1u 20u in parallel

                -Be careful adding large caps. Due to large size they usually have acoustic resonance frequencies in ~1MHz region. Good LDO will take less space than a large cap.

                 

                1. According to the "PSoC® 3 and PSoC 5LP External Oscillator - AN54439", I am able to attach an external oscillator (like TXCO) to the XtalIn so that the clock would route from MHzECO to the clock tree. If I power the PSoC5lp using 5V at Vdda and Vddd, could I use an 3.3V output TXCO?

                I believe that the external clock can be routed to any digital pin, not just to XTALin. To match 3.3V clock and 5V Vddd, I would try one of the SIO pins, which threshold can be adjusted to level other than CMOS, for example 1.02V or external 0.5 x 3.3V. That should work with 3.3V clock. The SIO configurations for digital input pin are shown below:

                Pins Annotation component for PSoC5 and PSoC4

                /odissey1

                • 6. Re: PSoC5lp External Clock voltage level, DelSig 1.2V reference, Vddio Vdda voltage relationship, decoupling capacitor values
                  HaJi_4128141

                  Hi BoTA,

                   

                  Thank you for your help!

                   

                  I will be careful of the caps.

                   

                  For the external clock, the reason that I want to put it at XTALin is to let the clock in as the MHzECO signal, so that I can save a digital clock signal route for other purposes, and maybe generate less noise internally in the chip? Since it does not route across the entire digital portion of the chip. But on the other hand, XTALin pin sits on the analog part of the chip, which means that the noise generated by the TXCO would have higher chance to migrate into the analog signal chain. I guess I will route it into a SIO as you suggested.

                   

                  Thanks again,

                  Hanpeng