1 2 Previous Next 27 Replies Latest reply on Oct 19, 2020 9:44 AM by MoPr_4537651

    PSoC 5LP latent shorts

    MoPr_4537651

      Hello,

       

      I recently designed custom hardware with PSoC as the main processor. Until the latest iteration I had no problems whatsoever. However, in this iteration, the hardware was perfectly working for a week and then 4 out of 5 boards randomly stopped working. The issue I found was that the PSoC was shorting Vcc and GND. I did a lot of debugging and analysis and then arrived at this conclusion. Initially I thought it was an issue with soldering. I ruled that out by removing all the components one by one and I was only left with the PSoC on the PCB and the short still existed. Once I removed the PSoC the short was no longer there. All the 4 boards had the exact same issue. Given below are my tests and observations

       

      1. I took the bad IC and put it on a new PCB. Vcc and GND started shorting there as well. That confirmed it was the PSoC causing the issue.

       

      2. I took a new IC and put in the old board which was initially shorting. There was no shorting anymore and the PCB started working again. This also confirmed that PSoC was causing the issue.

       

      3. I put the working PCB through a 24 hour test where it was continuously ON. The PCB draws about 140mA when fully functional. I wanted to see if the board gets overheated and the shorts were being caused due to that. But that wasn't the case. It successfully passed the test. The board was barely warm and it was properly working after that.

       

      4. I put the same PCB through a power cycling test. I switched on the supply for 30 seconds and then switched it off for 15 seconds. This pattern was continued for 24 hours. I was expecting some power surge or the frequent power discontinuities to have killed the PSoC. But it passed this test as well and the board is still working.

       

      5. I put it through an intense power cycling test for 1 hour. Here, I turned the supply on for 500ms and off for 500ms. This pattern was continued for 1 hour. The board was fully functional after this test too!

       

      6. I put the PCB through some violent motion to see if the mechanical stress and shock created the shorts. But that wasn't the case either. The PCB was fully functional after this test too!

       

      So in conclusion, I think I have ruled out thermal, power and mechanical stress/shock issues. What is the most likely reason for an issue like this where everything is fine for a week or so and then suddenly stops working?

       

      Please help me debug this issue. I am clueless at this point.

        • 1. Re: PSoC 5LP latent shorts
          LePo_1062026

          MoPr,

           

          Interesting problem.  It appears you have used a decent troubleshooting technique.   Like any troubleshooting session, you create a series of Design-of-Experiments (DoE).  The sad part, is you might not have found the 'magical' DoE to find the root cause. 

           

          Here are some thoughts that might lead to some additional DoEs.

           

          Thought #1 - Low-Level Thermal

          The issue appeared after one week.   This might be a low-grade thermal issue that occurs after many hours under the right condition.  It might be difficult to accelerate a thermal issue properly.   One way is to force the ambient temp for the PCB to the max allowed.   If you can put one or more PCBs into a temp chamber at the max operational temp for the IC (85C).   Any thermal related issues (even minor ones) should show up sooner.

           

          Thought #2 - What Changed?

          Did the FW change between iterations?

          Did the external HW circuit design change between iterations?

          When a fault starts appearing whereas it hadn't appeared before, I first ask: "What changed?"

          This for me is the first "go to" analysis of the issue.   Many times, the FW or HW (or both) that changed is a highlight to the root cause.

           

          Thought #3 - A bad IC from Cypress

          This is possible.  However, Cypress is a very reputable IC manufacturer with products for automotive and other critical industries.  This requires a discipline of proper design and testing processes in the development and manufacturing phases.   You might want to talk to a Cypress FAE about having them do an in-depth analysis which includes special Cypress-internal testing and if needed a "de-cap" of the IC to see damage of the silicon.   This can be helpful to identify the pin(s) involved.

           

          Thought #4 - Resistance testing across pins to determine the faulted pin(s)

          The proper way to perform testing about where the 'shorting' between Vcc and GND.  First on a 'bad' IC, resistance test between GND (VSSD, VSSA)  (- lead) and ALL PSoC pins (+ lead).  Next, you need to resistance test between Vcc (VDD, VDDD, VDDIO, VDDA) (+ lead) and ALL PSoC pins (- lead).   These results will be two columns in a pin matrix.

           

          Next perform the same resistance tests to Vcc and GND for a 'good' unused PSoC.   This becomes the next two columns in the matrix.

          With these 'bad" and 'good' results, you may be able to identify pins for the leakage path.   If the list of 'suspect' pins can be narrowed, you should reanalyze the external HW connected and the FW that would interact with these pins.

           

          Thought #5 - Static Voltage overstressing

          The IC allows input voltages up to the power source (VDD, VDDD, VDDIO, VDDA) +0.6V in the positive direction.   In the negative direction, -0.6V below GND (VSSD and VDDA) is allowed.

           

          It is possible an input may not be scaled or over-voltage protected.  In this case, it could be possible to damage the input.  The reason for the +0.6V to power and -0.6V to GND is that most PSoC have internal ESD protection diodes.   When the input exceeds the limits mentioned above, the diode is forward conducting.   Since these ESD diodes are physically small, forward biasing the diode with 25mA  or more of current can melt the diode junction causing what is called "input latchup".  It would be bad news for the input but can also for excess operating current.

           

          If this is the issue, you might need a slight redesign to minimize or mitigate the voltage overstress.

           

          Thought #6 - Transient Voltage overstressing

          The same reasoning listed in Though #5 applies here.  The difference is being able to monitor the transient will be a significant challenge.  Therefore, this exercise is more of a 'paper' analysis.   Having designs in the automotive industry, I have created PSpice simulations on the known industry transients before proceeding with the actual validation testing.

           

          Although the summer is generally less prone to ESD events, it is still possible.   Although there is some ESD protection on most pins, it may require some external mitigation.

           

          Thought #7 - Accidental or transient battery polarity reversal

          If the power supply (battery) polarity of VCC (VDD) and GND is short-term reversed, then Thought #5 applies across ALL ESD diodes and other internal circuits..

           

          In automotive where the power is supplied from the vehicle, we have to accommodate transient battery polarity reversals.  In this case, Though #6 applies to ALL ESD diodes and other internal circuits.

           

          Though #8 - The design "Oops"!

          It is not uncommon by a "newbie" or a "seasoned expert" a design "oops" is present.

          Good examples are:

          • Tying two or more external PSoC pins together with more than one pins as outputs at different logic states.   This is a undesirable condition and may that many hours before exhibiting long-term thermal damage to the output drivers.
          • Connecting a PSoC pin as output to an external circuit that drives the signal to the opposite logic direction.   This is why shared outputs should be set to drive in output drain (OD) mode with a pullup.   This is the common means of allowing multiple outputs on the signal at the same time.

           

          There may be other thoughts that I or others may be able to share.

          My goal for this 'wordy' post is for you or others monitoring this discussion to hopefully make benefit of my years of electronic design that I've learned "the hard way", (AKA "school of hard knocks", "bloodying my own nose") and from others insights.

           

          I hope your path to the root cause analysis is short.   In summary, if you can localize where in the IC the fault is, this will minimize the circuit analysis as well as creating your next DoE to prove the root cause and the eventual fix.

           

          Len

          • 2. Re: PSoC 5LP latent shorts
            EvPa_264126

            Make sure pin64 (Vssa) is connected to source ground.

            On My board, the analog ground had a separate contact and had to be jumpered to the common ground of the project.

            I forgot to install this jumper.

            Inside the chip CY8C5868AXI-LP035, pin64 (Vssa) and pin14 (Vssd) are connected, so I didn't notice the error.

            However, after a while the microcircuit got very hot, Vcc and GND closed.

            It doesn't seem to happen all the time, but right after the power is turned on.

            I'm not sure if this is your case but...

            • 3. Re: PSoC 5LP latent shorts
              MoPr_4537651

              Lepo,

               

              Thanks for the quick and elaborate reply

               

              LePo_1062026 wrote:

               

              MoPr,

               

              Interesting problem.  It appears you have used a decent troubleshooting technique.   Like any troubleshooting session, you create a series of Design-of-Experiments (DoE).  The sad part, is you might not have found the 'magical' DoE to find the root cause. 

               

              Here are some thoughts that might lead to some additional DoEs.

               

              Thought #1 - Low-Level Thermal

              The issue appeared after one week.   This might be a low-grade thermal issue that occurs after many hours under the right condition.  It might be difficult to accelerate a thermal issue properly.   One way is to force the ambient temp for the PCB to the max allowed.   If you can put one or more PCBs into a temp chamber at the max operational temp for the IC (85C).   Any thermal related issues (even minor ones) should show up sooner.

               

              That was actually next on my list! I should be done with it by this weekend. Will let you know how it goes.

               

              Thought #2 - What Changed?

              Did the FW change between iterations?

              Did the external HW circuit design change between iterations?

              When a fault starts appearing whereas it hadn't appeared before, I first ask: "What changed?"

              This for me is the first "go to" analysis of the issue.   Many times, the FW or HW (or both) that changed is a highlight to the root cause.

               

              Not much firmware changes.

               

              There were the following hardware changes.

              1. Replaced the -5V charge pump with a tinier and a better version.

              2. Changed one of the op-amps to a better one.

              3. BLE module was added on board instead of getting connected through wires.

               

              I highly doubt any of these would have caused the issues. In terms of power draw all of these are lower than before. No other red flags in these changes.

               

              Thought #3 - A bad IC from Cypress

              This is possible.  However, Cypress is a very reputable IC manufacturer with products for automotive and other critical industries.  This requires a discipline of proper design and testing processes in the development and manufacturing phases.   You might want to talk to a Cypress FAE about having them do an in-depth analysis which includes special Cypress-internal testing and if needed a "de-cap" of the IC to see damage of the silicon.   This can be helpful to identify the pin(s) involved.

               

              Oh, this is pretty interesting. How do I go about getting in contact with a FAE?

               

              Thought #4 - Resistance testing across pins to determine the faulted pin(s)

              The proper way to perform testing about where the 'shorting' between Vcc and GND.  First on a 'bad' IC, resistance test between GND (VSSD, VSSA)  (- lead) and ALL PSoC pins (+ lead).  Next, you need to resistance test between Vcc (VDD, VDDD, VDDIO, VDDA) (+ lead) and ALL PSoC pins (- lead).   These results will be two columns in a pin matrix.

               

              Next perform the same resistance tests to Vcc and GND for a 'good' unused PSoC.   This becomes the next two columns in the matrix.

              With these 'bad" and 'good' results, you may be able to identify pins for the leakage path.   If the list of 'suspect' pins can be narrowed, you should reanalyze the external HW connected and the FW that would interact with these pins.

               

              Ohh yes, this is very interesting. Will do this. This reminds me of one more weird thing I spotted.

               

              As long as the PSoC was on the PCB there was a short between Vcc and GND. However, when I removed the PSoC and then probed the supply and ground pins, I could not find any shorts. This just perplexed me even more! Why do you think that is happening?

               

              Thought #5 - Static Voltage overstressing

              The IC allows input voltages up to the power source (VDD, VDDD, VDDIO, VDDA) +0.6V in the positive direction.   In the negative direction, -0.6V below GND (VSSD and VDDA) is allowed.

               

              It is possible an input may not be scaled or over-voltage protected.  In this case, it could be possible to damage the input.  The reason for the +0.6V to power and -0.6V to GND is that most PSoC have internal ESD protection diodes.   When the input exceeds the limits mentioned above, the diode is forward conducting.   Since these ESD diodes are physically small, forward biasing the diode with 25mA  or more of current can melt the diode junction causing what is called "input latchup".  It would be bad news for the input but can also for excess operating current.

               

              If this is the issue, you might need a slight redesign to minimize or mitigate the voltage overstress.

               

              Thought #6 - Transient Voltage overstressing

              The same reasoning listed in Though #5 applies here.  The difference is being able to monitor the transient will be a significant challenge.  Therefore, this exercise is more of a 'paper' analysis.   Having designs in the automotive industry, I have created PSpice simulations on the known industry transients before proceeding with the actual validation testing.

               

              Although the summer is generally less prone to ESD events, it is still possible.   Although there is some ESD protection on most pins, it may require some external mitigation.

               

              The PSoC is being supplied through an external voltage regulator. I probed the supply voltage and recorded it for 24 hours to see if there was any undervoltage, voltage or transients happening. Nothing of that sort happened. It was pretty stable. Yeah true, ESD is definitely one of the possibilities. If thermal cycling  goes well, I'm guessing ESD is the only thing left?

               

              Thought #7 - Accidental or transient battery polarity reversal

              If the power supply (battery) polarity of VCC (VDD) and GND is short-term reversed, then Thought #5 applies across ALL ESD diodes and other internal circuits..

               

              In automotive where the power is supplied from the vehicle, we have to accommodate transient battery polarity reversals.  In this case, Though #6 applies to ALL ESD diodes and other internal circuits.

               

              Currently, it's only me and one other person operating this device. I am pretty confident that neither of us connected the battery in reverse. However, thoughts #5 , #6 and #7 are serious issues. I was anyway planning to add it to the PCB once the rest of the circuit was working well. Now that I have crossed that stage, I am looking at adding undervoltage lockout, overvoltage lockout, overcurrent lockout, reverse polarity protection and ESD protection to the PCB. On that note, I was planning on using LTC4362-2 along with an external SI2323DS MOSFET for those purposes. What do you think about that? Will that be sufficient?

               

              Though #8 - The design "Oops"!

              It is not uncommon by a "newbie" or a "seasoned expert" a design "oops" is present.

              Good examples are:

              • Tying two or more external PSoC pins together with more than one pins as outputs at different logic states.   This is a undesirable condition and may that many hours before exhibiting long-term thermal damage to the output drivers.
              • Connecting a PSoC pin as output to an external circuit that drives the signal to the opposite logic direction.   This is why shared outputs should be set to drive in output drain (OD) mode with a pullup.   This is the common means of allowing multiple outputs on the signal at the same time.

               

              Yeah, that's very true. However, I do not have any shared outputs, so this shouldn't be an issue.

               

              There may be other thoughts that I or others may be able to share.

              My goal for this 'wordy' post is for you or others monitoring this discussion to hopefully make benefit of my years of electronic design that I've learned "the hard way", (AKA "school of hard knocks", "bloodying my own nose") and from others insights.

               

              Your reply has been really insightful. This is the first time I am facing this kind of a reliability issue. Really helps to have someone experienced share their knowledge.

               

              I hope your path to the root cause analysis is short.   In summary, if you can localize where in the IC the fault is, this will minimize the circuit analysis as well as creating your next DoE to prove the root cause and the eventual fix.

               

              I hope so too! Let's see how the thermal cycling test goes.

               

              Len

               

              Thanks again!

              Mohan Prabhakar

               

              P.S: I replied to your thoughts inline. But I don't think it is differentiating my reply from your original text. Please read through my replies, I have a few more questions I put in there

              • 4. Re: PSoC 5LP latent shorts
                MoPr_4537651

                Evgeniy,

                 

                I am using the CY8C5888LIT-LP097 chip of the family. I used a minimized version of the official CY8CKIT-059 schematic to build this. However, I do have a similar situation in mine. There are 2 VCCD pins shorted internally (Pins 26 and 57). I haven't connected those two pins externally since I did not face any issue even with the previous iterations. Moreover those pins are left unused. Right now they have just been connected to ground through a decoupling capacitor. Should I still connect those two pins externally?

                 

                Thanks

                Mohan Prabhakar 

                • 5. Re: PSoC 5LP latent shorts
                  EvPa_264126

                  Pins 26 and 57 are VCCD and only capacitors are connected to them.

                  However, in PSoC® 5LP: CY8C58LP Family Datasheet page 11

                  indicated that the VCCD pins must be connected with an external conductor.

                  I meant something else: the VSSA (LP095) contact apparently also has an internal connection with

                  VSSD but this is not just a jumper but something else that requires a mandatory external connection.

                  In your case (LP097) these are the VSSA pins (pin 43) and VCCD ((pin 9)).

                  They must be connected with a conductor

                  • 6. Re: PSoC 5LP latent shorts
                    LePo_1062026

                    MoPr,

                     

                    Thought #2 - What Changed?

                    ...

                    Not much firmware changes.

                     

                    There were the following hardware changes.

                    1. Replaced the -5V charge pump with a tinier and a better version.

                    I don't know how the -5V charge pump interfaces to the PSoC.   Verify there is enough isolation between the 5V and -5V sides.

                    ...

                    3. BLE module was added on board instead of getting connected through wires.

                    Interesting.  Many BLE devices require a max of 3.3V for VDD.  What is the voltage of your PSoC? 5V?

                     

                    Thought #3 - A bad IC from Cypress

                    ...

                    Oh, this is pretty interesting. How do I go about getting in contact with a FAE?

                    Contact Cypress/Infineon sales in your area.  (I don't know where you're located).

                    Sales Contact

                    Franchised Distributors

                    International Sales Offices

                    North American Sales Offices

                     

                    Thought #4 - Resistance testing across pins to determine the faulted pin(s)

                    ...

                     

                    ... This reminds me of one more weird thing I spotted.

                     

                    As long as the PSoC was on the PCB there was a short between Vcc and GND. However, when I removed the PSoC and then probed the supply and ground pins, I could not find any shorts. This just perplexed me even more! Why do you think that is happening?

                    Now I have to ask.  What evidence do you have that there is a short between VCC and GND?

                    You will notice Thought #5 and #6 mention a input latchup condition on ESD diodes that have forward conducted with too much current.  If this is the case, Vcc (VDD, VDDD, VDDIO or VDDA) or GND (VSSD, VSSA) may not show a 'short'.  This condition might only show up on the damaged pin.

                     

                    Note:  Meter polarity on your resistance measurements are CRITICAL!   The resistance on some pins will be different from + to - compared to - to +.

                     

                    Thought #6 - Transient Voltage overstressing

                    ...

                    The PSoC is being supplied through an external voltage regulator. I probed the supply voltage and recorded it for 24 hours to see if there was any undervoltage, voltage or transients happening. Nothing of that sort happened. It was pretty stable. Yeah true, ESD is definitely one of the possibilities. If thermal cycling  goes well, I'm guessing ESD is the only thing left?

                    Monitoring random transients can be very challenging.   Many years ago it took me two weeks to catch a particular transient as the beginning of the root cause.

                     

                    Thought #7 - Accidental or transient battery polarity reversal

                    ...

                     

                    Currently, it's only me and one other person operating this device. I am pretty confident that neither of us connected the battery in reverse. However, thoughts #5 , #6 and #7 are serious issues. I was anyway planning to add it to the PCB once the rest of the circuit was working well. Now that I have crossed that stage, I am looking at adding undervoltage lockout, overvoltage lockout, overcurrent lockout, reverse polarity protection and ESD protection to the PCB. On that note, I was planning on using LTC4362-2 along with an external SI2323DS MOSFET for those purposes. What do you think about that? Will that be sufficient?

                     

                    I don't know what your source voltage is.  Since I have worked in automotive, there are standards and circuits to use to prevent weird voltage conditions including transients.   Your use of LTC4362-2 along with an external SI2323DS MOSFET sound about correct.

                     

                    Though #8 - The design "Oops"!

                    ...

                    Yeah, that's very true. However, I do not have any shared outputs, so this shouldn't be an issue.

                    Good.  There could be other 'oopsies'.  Too many to name here.

                     

                    The goal is to isolate where the 'fault' is.   Is it on the Power Pin (VDD,GND) structure or is it only on one or more pins?

                    When this condition occurs on the 4 out of 5 boards, what parts of the board are working or at least in-spec?   What part(s) are NOT working?

                     

                    Thought #4 is a good DoE but can take a long time to measure.

                     

                    In my opinion, getting a 'bad' part from Cypress is least likely. If it is a 'bad' IC from Cypress, it would be more likely to be a bad lot.

                     

                    Len

                    • 7. Re: PSoC 5LP latent shorts
                      MoPr_4537651

                      Ohh, thanks for the clarification. Those two pins have been connected properly

                      • 8. Re: PSoC 5LP latent shorts
                        MoPr_4537651

                        LePo_1062026 wrote:

                         

                        MoPr,

                         

                        Thought #2 - What Changed?

                        ...

                        Not much firmware changes.

                         

                        There were the following hardware changes.

                        1. Replaced the -5V charge pump with a tinier and a better version.

                        I don't know how the -5V charge pump interfaces to the PSoC.   Verify there is enough isolation between the 5V and -5V sides.

                        ...

                        3. BLE module was added on board instead of getting connected through wires.

                        Interesting.  Many BLE devices require a max of 3.3V for VDD.  What is the voltage of your PSoC? 5V?

                         

                        The -5V is only for the opamps. It does not come in direct contact with the PSoC at all.

                         

                        I am supplying the PSoC through a 3.3V regulator with an inbuilt current limiter of 200mA. Same thing goes to the BLE as well through a load switch.

                         

                        Thought #3 - A bad IC from Cypress

                        ...

                        Oh, this is pretty interesting. How do I go about getting in contact with a FAE?

                        Contact Cypress/Infineon sales in your area.  (I don't know where you're located).

                        Sales Contact

                        Franchised Distributors

                        International Sales Offices

                        North American Sales Offices

                         

                        Thanks a lot. Will look into it

                        Thought #4 - Resistance testing across pins to determine the faulted pin(s)

                        ...

                         

                        ... This reminds me of one more weird thing I spotted.

                         

                        As long as the PSoC was on the PCB there was a short between Vcc and GND. However, when I removed the PSoC and then probed the supply and ground pins, I could not find any shorts. This just perplexed me even more! Why do you think that is happening?

                        Now I have to ask.  What evidence do you have that there is a short between VCC and GND?

                        You will notice Thought #5 and #6 mention a input latchup condition on ESD diodes that have forward conducted with too much current.  If this is the case, Vcc (VDD, VDDD, VDDIO or VDDA) or GND (VSSD, VSSA) may not show a 'short'.  This condition might only show up on the damaged pin.

                         

                        Note:  Meter polarity on your resistance measurements are CRITICAL!   The resistance on some pins will be different from + to - compared to - to +.

                         

                        I did a continuity test on the decoupling capacitors. All of them connected to 3.3V and GND were shorted. The shorts vanished both on the PCB and the PSoC the moment I removed the PSoC from the PCB like I mentioned in my original post. Thanks for that Note, will keep that in mind.

                         

                        Thought #6 - Transient Voltage overstressing

                        ...

                        The PSoC is being supplied through an external voltage regulator. I probed the supply voltage and recorded it for 24 hours to see if there was any undervoltage, voltage or transients happening. Nothing of that sort happened. It was pretty stable. Yeah true, ESD is definitely one of the possibilities. If thermal cycling  goes well, I'm guessing ESD is the only thing left?

                        Monitoring random transients can be very challenging.   Many years ago it took me two weeks to catch a particular transient as the beginning of the root cause.

                         

                        Ohh wow. That's quite tedious and challenging.

                         

                        Thought #7 - Accidental or transient battery polarity reversal

                        ...

                         

                        Currently, it's only me and one other person operating this device. I am pretty confident that neither of us connected the battery in reverse. However, thoughts #5 , #6 and #7 are serious issues. I was anyway planning to add it to the PCB once the rest of the circuit was working well. Now that I have crossed that stage, I am looking at adding undervoltage lockout, overvoltage lockout, overcurrent lockout, reverse polarity protection and ESD protection to the PCB. On that note, I was planning on using LTC4362-2 along with an external SI2323DS MOSFET for those purposes. What do you think about that? Will that be sufficient?

                         

                        I don't know what your source voltage is.  Since I have worked in automotive, there are standards and circuits to use to prevent weird voltage conditions including transients.   Your use of LTC4362-2 along with an external SI2323DS MOSFET sound about correct.

                         

                        My voltage source is a single cell LiPo battery. Thanks, will go ahead with this.

                        Though #8 - The design "Oops"!

                        ...

                        Yeah, that's very true. However, I do not have any shared outputs, so this shouldn't be an issue.

                        Good.  There could be other 'oopsies'.  Too many to name here.

                         

                        The goal is to isolate where the 'fault' is.   Is it on the Power Pin (VDD,GND) structure or is it only on one or more pins?

                        When this condition occurs on the 4 out of 5 boards, what parts of the board are working or at least in-spec?   What part(s) are NOT working?

                         

                        Everything else was working the way it was supposed to. Only the PSoC was the issue. Once I replaced the PSoC on the PCB things went back to normal.

                         

                        Thought #4 is a good DoE but can take a long time to measure.

                         

                        Agreed.

                         

                        In my opinion, getting a 'bad' part from Cypress is least likely. If it is a 'bad' IC from Cypress, it would be more likely to be a bad lot.

                         

                        Hmm yeah, makes sense. I did order 5 ICs from mouser and 4 of those were bad. So possibly a bad lot?

                         

                        Len

                        • 9. Re: PSoC 5LP latent shorts
                          LePo_1062026

                          MoPr,

                           

                          I did a continuity test on the decoupling capacitors. All of them connected to 3.3V and GND were shorted. The shorts vanished both on the PCB and the PSoC the moment I removed the PSoC from the PCB like I mentioned in my original post.

                           

                          Hmm.  Interesting.  Continuity tests with a meter can be tricky.  The way the meter makes the measurement is that it sources a known accurate reference current (like 1mA).   With the current present, it measures the voltage across the = and - probes.   Then Runknown = Vmeasured/Iref.   The tricky part is that caps look like a short initially.  As the cap charges from the current source, it looks less like a short and gains 'resistance'. 

                           

                          It is possible that the 'short' you are seeing isn't on the VDD, VDDD, VDDIO, VDDA, VSSD and VSSA pins directly.  It could be due to a damaged pin.  Remember the ESD diodes I mentioned.  If one (or both) of the ESD diodes on an input are damaged, it could look like a short between the power pin and GND pin.

                           

                          Do you get the unshorted condition in the decoupling caps on the 1 out of 5 boards still working?

                           

                          Len

                          • 10. Re: PSoC 5LP latent shorts
                            MoPr_4537651

                            LePo_1062026 wrote:

                             

                            MoPr,

                             

                            I did a continuity test on the decoupling capacitors. All of them connected to 3.3V and GND were shorted. The shorts vanished both on the PCB and the PSoC the moment I removed the PSoC from the PCB like I mentioned in my original post.

                             

                            Hmm.  Interesting.  Continuity tests with a meter can be tricky.  The way the meter makes the measurement is that it sources a known accurate reference current (like 1mA).   With the current present, it measures the voltage across the = and - probes.   Then Runknown = Vmeasured/Iref.   The tricky part is that caps look like a short initially.  As the cap charges from the current source, it looks less like a short and gains 'resistance'.

                             

                            Yeah agreed. I initially do get a short for a fraction of a second and then the meter stops beeping.

                             

                            It is possible that the 'short' you are seeing isn't on the VDD, VDDD, VDDIO, VDDA, VSSD and VSSA pins directly.  It could be due to a damaged pin.  Remember the ESD diodes I mentioned.  If one (or both) of the ESD diodes on an input are damaged, it could look like a short between the power pin and GND pin.

                             

                            Ohh ok, that makes sense.

                             

                            Do you get the unshorted condition in the decoupling caps on the 1 out of 5 boards still working?

                             

                            Yup, I do get the unshorted condition on the board that is still working.

                             

                            Len

                            • 11. Re: PSoC 5LP latent shorts
                              AH_96

                              Hi MoPr_4537651

                               

                              Would it be possible to share the schematic of your design?

                              What is the voltage level that you are observing at the VCC pin in the PCB with the good PSoC connected?

                               

                              Thanks,

                              Hari

                              • 12. Re: PSoC 5LP latent shorts
                                MoPr_4537651

                                Hello Hari,

                                 

                                Sorry I won't be able to share the whole schematic as it's part of an ongoing product development. If you can tell me what you are looking for I will be more than happy to share the relevant parts of the schematics.

                                 

                                Right now I am observing 3.3V as expected in the good PCB.

                                 

                                Mohan Prabhakar

                                • 13. Re: PSoC 5LP latent shorts
                                  AH_96

                                  Hi Mohan,

                                   

                                  Mohan Prabhakar wrote:

                                   

                                  Hello Hari,

                                   

                                  Sorry I won't be able to share the whole schematic as it's part of an ongoing product development. If you can tell me what you are looking for I will be more than happy to share the relevant parts of the schematics.

                                  I understand.

                                   

                                  Right now I am observing 3.3V as expected in the good PCB.

                                  This is bad. We expect the core logic to be only 1.8V. 3.3V on the VCC pin can potentially damage the device. Please let me know if you are shorting the VDD and VCC pins. If so, this must not be done.

                                  I saw in an earlier response that you had stated you are connecting only the decoupling capacitor to the VCC pin which is correct. The reason for this 3.3V needs to be understood as this is likely causing the failure that you are seeing.

                                   

                                  1. Are you shorting the two VCCD pins externally?

                                  2. Is there any connection between the VCC pin and VDD or any other higher voltage?

                                  3. Without the PSoC in place, what is the voltage at VCC pin when the power is supplied to the board?

                                   

                                  Best regards,
                                  Hari

                                  • 14. Re: PSoC 5LP latent shorts
                                    MoPr_4537651

                                    AH_96 wrote:

                                     

                                    Hi Mohan,

                                     

                                    Mohan Prabhakar wrote:

                                     

                                    Hello Hari,

                                     

                                    Sorry I won't be able to share the whole schematic as it's part of an ongoing product development. If you can tell me what you are looking for I will be more than happy to share the relevant parts of the schematics.

                                    I understand.

                                     

                                    Right now I am observing 3.3V as expected in the good PCB.

                                    This is bad. We expect the core logic to be only 1.8V. 3.3V on the VCC pin can potentially damage the device. Please let me know if you are shorting the VDD and VCC pins. If so, this must not be done.

                                    I saw in an earlier response that you had stated you are connecting only the decoupling capacitor to the VCC pin which is correct. The reason for this 3.3V needs to be understood as this is likely causing the failure that you are seeing.

                                     

                                    Sorry, I misunderstood your question. I thought you meant the general supply voltage when you said Vcc. There is no supply going to the VCCx pins. I am operating the PSoC in regulated mode, so my supply is going to VDDx pins.

                                     

                                    1. Are you shorting the two VCCD pins externally?

                                    No.

                                    2. Is there any connection between the VCC pin and VDD or any other higher voltage?

                                    No.

                                    3. Without the PSoC in place, what is the voltage at VCC pin when the power is supplied to the board?

                                    0V.

                                     

                                    Best regards,
                                    Hari

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