1 Reply Latest reply on Sep 21, 2020 2:37 AM by ApurvaS_36

    Interfacing PSoC 6 BLE chip with an external SRAM

    dekr_4738561

      Hello,

                I am working on a design that requires additional external RAM in excess of what is available (288 KB) on the CY8C6347FMI-BLD53T.

      I am particularly interested in utilizing the octal SPI interface on the PSoC 6. Due to current part stocking issues, I was unable to find an SRAM that runs at 3.3V (the PSoC 6 is configured for 3.3V in my design). The chip I finally decided to use runs at 1.8V and is the 64Mb S27KS0643GABHV020.

       

      However, it says on the data sheet for the Pseudo SRAM, that the differential clock is optional and the CK# need not be used. It does clearly say that the 3.0V chip in the same family, uses a single-ended clock. Since the PSoC6 generates a single-ended clock output on its SMIF interface that supports octal SPI, I was not sure if I really needed a single-ended to differential converter for the same. My initial research led to utilizing an LTC6403-1 fully differential driver on the board. Since I have design constraints, and the system on board runs at 3.3V, I needed to add a 1.8v regulator in the mix as well. But that’s pretty much the extent to which I can add components to my system (I have level shifters for the 3.3v to 1.8v conversion on the data lines and the additional CS, RWDS lines).

       

      So I have few questions:

       

      1. Does the external Pseudo SRAM (S27KS0643GABHV020) I selected really need a differential clock? Can I make do with a single ended clock input from the PSoC 6?

      2. What part is recommended for level shifting a clock output from 3.3V to 1.8V?

      3. If it is mandatory to have a differential clock, what part is recommended for single ended to differential clock conversion in my current setup?

       

      Thanks in advance.

        • 1. Re: Interfacing PSoC 6 BLE chip with an external SRAM
          ApurvaS_36

          Hi,

           

          Thank you for contacting Cypress Community.

           

          1. Differential clock is optional. You can choose whether you want to use it or not. If you go to page 24 of the datasheet you will see that bit [6] of the Configuration Register 1 controls the master clock type. The good thing is that the default is already set to single ended clock.
          2. I don't think we make a level shifting recommendation here. It just needs to be fast enough to follow the signals at high speed like 200MHz which this part is able to run at. Also, if you don't have a temperature grade/speed limitation then you can choose to use the S27KL0643xxxxx020 part that supports 3.3V.
          3. As stated before, differential clock is not mandatory.

           

          Thank you and Regards,

          Apurva