1 Reply Latest reply on Sep 21, 2020 8:04 PM by XiaoweiZ_71

    In PSoC6, PDL can not clear the IIC bus underflow interrupt

    shyo_2565646

      dear sir:

             when we develop our software use PSOC6, we meet the following problem.

      <software description>

      we use 2 channel I2C of PSOC6, one channel is for control device1, the other channel is for control device2.

      <problem>

      The waveform when the normal action

      Channel0: I2C1 data ;  Channel1: I2C1 clk ; Channel2: I2C2 data ; Channel3: I2C2 clk

      Channel4: test pin (any i2c channel1  interrupt occur, put to High, interrupt finished, put to low)

      Channel5: test pin (i2c channel1 underflow interrupt occur, put to High, interrupt finished put to low)

       

      very low appearance, the following waveform appear.

       

      When the error waveform appear,

      we send the chip address with write bit  ---  0x9C,

      because I2C2 is during transmitting , so the interrupt of I2C1 is delayed.(Channel 4 , first high level)

      but during the interrupt process, set the next data(0x73),

      Why the underflow interrupt occur ?(channel 5 high level)

       

      <Comment>

      We used the PDL Ver 3.1.2.

       

      we analyze the PDL source code.

      we found that

      in Cy_scb_i2c.c  line2914, function : MasterHandleDataTransmit,

      line 2947:  Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UNDERFLOW);

      Can not clear the underflow interrupt.

       

      but if we call the function again, we can clear the interrupt.

       

      in other words:

      [  intrStatus = Cy_SysLib_EnterCriticalSection();

         Cy_SCB_WriteTxFifo     (base, (uint32_t) context->masterBuffer[0UL]);

         Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UNDERFLOW);

         Cy_SysLib_ExitCriticalSection(intrStatus);   ]

      can not clear the underflow interrupt.

       

      [  intrStatus = Cy_SysLib_EnterCriticalSection();

         Cy_SCB_WriteTxFifo     (base, (uint32_t) context->masterBuffer[0UL]);

         Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UNDERFLOW);

         Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UNDERFLOW);

         Cy_SysLib_ExitCriticalSection(intrStatus);   ]

      can clear the underflow interrupt.

       

      can you please tell me the reason?

       

      best regards, and many thanks

        • 1. Re: In PSoC6, PDL can not clear the IIC bus underflow interrupt
          XiaoweiZ_71

          首先  I2C2的工作状态与 I2C1以及其中断的产生时间应该没有关系,每个 SCB 以及其中断都是完全独立的,相互之间并不存在耦合或资源共享。我建议你在两个中断函数中对两个test pin 分别改成做 toggle 操作,这样就比较容易看出这个中断产生的时机和具体次数,我比较怀疑 UNDERFLOW 中断在短时间内可能产生了多次,清一次中断只能清楚中断状态寄存器中的标志位,但是中断锁存 buffer 中应该还有未响应的中断。

           

          你方便提供可以复现问题的Creator 工程吗?