1 2 Previous Next 21 Replies Latest reply on Sep 25, 2020 12:16 AM by JeHa_4771251

    HT Avail timeout w/Murata 43012 1LV on Xilinx ZynqMP

    JeHa_4771251

      Hello,

       

        We have custom board with a 43012 connected via SDIO to a Xilinx ZynqMP.    We are using the latest Xilinx release which run the 5.4.0 kernel.   Based on information in the v5.4.18-2020_0625 version of the backport driver and cypress-yocto-scripts I have added support into yocto to build everything.

       

       

        I am using the following firmware/nvram files:

      BCM43012C0_003.001.015.0102.0141.1LV.hcd*  brcmfmac43012-sdio.1LV.txt  cyfmac43012-sdio.bin  cyfmac43012-sdio.clm_blob

       

      I get the timeout error so the wlan0 interface is never created.

       

      Based on the kernel logs the chip is powered up and the driver can talk to it.

       

      ================================================================

      [   12.985101] brcmfmac: brcmf_sdio_kso_init Enter

      [   12.985117] brcmfmac: brcmf_sdio_drivestrengthinit No SDIO driver strength init needed for chip BCM43012/2 rev 2 pm0

      [   12.985353] brcmfmac: brcmf_sdio_probe completed!!

      [   12.985359] brcmfmac: brcmf_fw_alloc_request: using cypress/cyfmac43012-sdio for chip BCM43012/2

      [   12.994144] brcmfmac: brcmf_fw_get_firmwares enter: dev=mmc1:0001:1

      [   12.994149] brcmfmac: brcmf_ops_sdio_probe F2 init completed...

      [   12.994254] usbcore: registered new interface driver brcmfmac

      [   13.000643] brcmfmac: brcmf_fw_complete_request firmware cypress/cyfmac43012-sdio.bin found

      [   13.000692] brcmfmac mmc1:0001:1: Direct firmware load for cypress/cyfmac43012-sdio.xlnx,zynqmp.txt failed with err2

      [   13.011657] brcmfmac: brcmf_fw_complete_request firmware cypress/cyfmac43012-sdio.txt found

      [   13.011662] brcmfmac: brcmf_fw_request_nvram_done enter: dev=mmc1:0001:1

      [   13.011690] brcmfmac: brcmf_nvram_handle_key warning: ln=33:col=10: '=' expected, skip invalid key entry

      [   13.011788] brcmfmac: brcmf_fw_request_nvram_done nvram 00000000d6229003 len 2356

      [   13.011796] brcmfmac: brcmf_sdio_clkctl Enter

      [   13.011798] brcmfmac: brcmf_sdio_htclk Enter

      [   13.011849] brcmfmac: brcmf_sdio_htclk CLKCTL: turned ON

      [   13.011852] brcmfmac: brcmf_sdio_clkctl 1 -> 3

      [   13.011856] brcmfmac: brcmf_sdio_download_firmware firmware rstvec: 0

      [   13.011858] brcmfmac: brcmf_sdio_download_code_file Enter

      .

      .

      [   13.070357] brcmfmac: brcmf_sdio_download_nvram Enter

      [   13.070399] brcmfmac: brcmf_sdiod_ramrw write 2356 bytes at offset 0x000076cc in window 0x00098000

      [   13.070581] brcmfmac: brcmf_sdio_verifymemory Compare RAM dl & ul at 0x0009f6cc; size=2356

      [   13.070586] brcmfmac: brcmf_sdiod_ramrw read 2048 bytes at offset 0x000076cc in window 0x00098000

      [   13.070711] brcmfmac: brcmf_sdiod_ramrw read 308 bytes at offset 0x00007ecc in window 0x00098000

      [   13.070755] brcmfmac: brcmf_chip_set_active Enter

      [   13.071159] brcmfmac: brcmf_sdio_clkctl Enter

      [   13.071161] brcmfmac: brcmf_sdio_htclk Enter

      [   13.071177] brcmfmac: brcmf_sdio_htclk CLKCTL: turned OFF

      [   13.071180] brcmfmac: brcmf_sdio_clkctl 3 -> 1

      [   13.071185] brcmfmac: brcmf_sdio_clkctl Enter

      [   13.071187] brcmfmac: brcmf_sdio_htclk Enter

      [   14.072857] brcmfmac: brcmf_sdio_htclk: HT Avail timeout (1000000): clkctl 0x50

      [   14.080236] brcmfmac: brcmf_sdio_clkctl 1 -> 1

      [   14.080244] brcmfmac: brcmf_sdio_firmware_callback failed: dev=mmc1:0001:1, err=0

      [   14.080268] brcmfmac: brcmf_ops_sdio_remove Enter

      ======================================================================

       

      It appears that the firmware is loaded and the nvram.  However, after the nvram is loaded and this code from brcmf_sdio_htclk is executed I get the timeout error.

       

      /* Otherwise, wait here (polling) for HT Avail */

      timeout = jiffies +

        msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);

      while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {

        clkctl = brcmf_sdiod_readb(bus->sdiodev,

         SBSDIO_FUNC1_CHIPCLKCSR,

         &err);

        if (time_after(jiffies, timeout))

          break;

        else

         usleep_range(5000, 10000);

        }

        if (err) {

          brcmf_err("HT Avail request error: %d\n", err);

          return -EBADE;

        }

        if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {

          brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",

            PMU_MAX_TRANSITION_DLY, clkctl);

         return -EBADE;

      }

       

      It looks like the the code is trying to re-initialize certain things after loading the nvram and what looks like a status register, SBSDIO_FUNC1_CHIPCLKCSR, has an error it it.

       

      Any ideas of what could be happening here?  Is this process trying to switch from an internal to external clock?   We do have an external osc. connected to EXT_LPO.  I know it's unlikely, but is there any available documentation that would describe SBSDIO_FUNC1_CHIPCLKCSR?

       

      thanks

      jeff

        • 1. Re: HT Avail timeout w/Murata 43012 1LV on Xilinx ZynqMP
          ZhengbaoZ_96

          Hello:

           

             Would you please upload your brcmfmac43012-sdio.1LV.txt ? and are you using sdio in-band interrupt for 43012?

          • 2. Re: HT Avail timeout w/Murata 43012 1LV on Xilinx ZynqMP
            JeHa_4771251

            Hello,

             

            I have attached the nvram file.  Note this does have the changes I just tried, setting bit 27 of boardflags3 since we have a external crystal(no change in behavior).  I got this file from the nvram.zip from the cypress-yocto-scripts-v5.4.18-2020_0625 tarball.

             

            It uses the in-band interrupt by default, right?  I have not done anything specific dealing with that or trying to drive WL_HOST_WAKE.  Here is my devicetree entry if that helps.

             

            &sdhci1 {

                status = "okay";

                #address-cells = <1>;

                #size-cells = <0>;

                bus-width = <4>;

                no-1-8-v;       /* force 3.3V VIO */

                non-removable;

                mmc-pwrseq = <&sdhci1_pwrseq>;

                pm-ignore-notify;

                cap-power-off-card;

                /*max-frequency = <25000000>;*/

                brcmf: bcrmf@1 {

                    reg = <1>;

                    compatible = "brcm,bcm4329-fmac";

                };

            };

             

            thank you,

            jeff

            • 3. Re: HT Avail timeout w/Murata 43012 1LV on Xilinx ZynqMP
              ZhengbaoZ_96

              # muxenab defined to enable OOB IRQ. Level sensitive interrupt via WL_HOST_WAKE line.

              muxenab=0x01

               

              it used OOB interrupt as default.

              You can comment this line and add below setting to see if INT can work normally.

              sd_gpout=0

              sd_oobonly=1

              sd_gpval=1

              sd_gpdc=0

              • 4. Re: HT Avail timeout w/Murata 43012 1LV on Xilinx ZynqMP
                JeHa_4771251

                Hello,

                 

                 

                Thank you for your response.   I did try the changes you suggested but it still did not work.

                 

                #muxenab=0x01

                sd_gpout=0

                sd_oobonly=1

                sd_gpval=1

                sd_gpdc=0

                 

                I tried with and without bit 27 of boardflags3 set since I did not know what was correct.

                 

                Should in-band interrupt work? I looked at our schematic again and we go have WL_HOST_WAKE connected but I do not have anything defined in the devicetree?

                 

                jeff

                • 5. Re: HT Avail timeout w/Murata 43012 1LV on Xilinx ZynqMP
                  ZhengbaoZ_96

                  copy one INT in the other DTS , this has a OOB setting.

                   

                  &usdhc3 {

                  #address-cells = <1>;

                  #size-cells = <0>;

                  pinctrl-names = "default";

                  pinctrl-0 = <&pinctrl_wifi>;

                  bus-width = <4>;

                  no-1-8-v; /* force 3.3V VIO */

                  non-removable;

                  mmc-pwrseq = <&usdhc3_pwrseq>;

                  pm-ignore-notify;

                  cap-power-off-card;

                  status = "okay";

                   

                   

                  brcmf: bcrmf@1 {

                  reg = <1>;

                  compatible = "brcm,bcm4329-fmac";

                  interrupt-parent = <&gpio6>;

                  interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;

                  interrupt-names = "host-wake";

                  };

                  };

                  • 6. Re: HT Avail timeout w/Murata 43012 1LV on Xilinx ZynqMP
                    JeHa_4771251

                    I have an external crystal connected to EXT_LPO should is use boardflags3=0x48000100 or boardflags3=0x40000100 ?

                     

                    I have added the interrupt to my DT but it is never enabled.  After the FW and NVRAM are is loaded successfully, brcmf_sdio_firmware_callback has this code

                     

                        /* Make sure backplane clock is on, needed to generate F2 interrupt */

                        brcmf_sdio_clkctl(bus, CLK_AVAIL, false);

                        if (bus->clkstate != CLK_AVAIL)

                            goto release;

                     

                     

                    And from the kernel logs:

                    [   13.077158] brcmfmac: brcmf_sdio_htclk Enter

                    [   14.085079] brcmfmac: brcmf_sdio_htclk: HT Avail timeout (1000000): clkctl 0x50

                    [   14.092420] brcmfmac: brcmf_sdio_clkctl 1 -> 1

                    [   14.092428] brcmfmac: brcmf_sdio_firmware_callback failed: dev=mmc1:0001:1, err=0

                     

                    It looks like the code is trying to turn the backplane/HT clock back on after loading the firmware and it is failing.

                     

                    jeff

                    • 7. Re: HT Avail timeout w/Murata 43012 1LV on Xilinx ZynqMP
                      ZhengbaoZ_96

                      for external LPO, I think it is the right value.

                      boardflags3=0x48000100

                      • 8. Re: HT Avail timeout w/Murata 43012 1LV on Xilinx ZynqMP
                        JeHa_4771251

                        OK, that is the setting I'm using.

                         

                        But the problem still is not with the OOB interrupt since that has not even been initialized yet.  The code is writing SBSDIO_ALP_AVAIL_REQ to SBSDIO_FUNC1_CHIPCLKCSR  and the status register never returns that HT Avail is ready.    I can't understand what the chip is looking for???

                         

                         

                         

                                /* Request HT Avail */

                                clkreq =

                                    bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;

                         

                                brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,

                                           clkreq, &err);

                         

                        .

                        .

                        .

                        .

                         

                                        /* Otherwise, wait here (polling) for HT Avail */

                                        timeout = jiffies +

                                                  msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);

                                        while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {

                                                clkctl = brcmf_sdiod_readb(bus->sdiodev,

                                                                           SBSDIO_FUNC1_CHIPCLKCSR,

                                                                           &err);

                                                if (time_after(jiffies, timeout))

                                                        break;

                                                else

                                                        usleep_range(5000, 10000);

                                        }

                                        if (err) {

                                                brcmf_err("HT Avail request error: %d\n", err);

                                                return -EBADE;

                                        }

                                        if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {

                                                brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",

                                                          PMU_MAX_TRANSITION_DLY, clkctl);

                                                return -EBADE;

                                        }

                        • 9. Re: HT Avail timeout w/Murata 43012 1LV on Xilinx ZynqMP
                          ZhengbaoZ_96

                          So your steps are :

                           

                          Copy brcmfmac43012-sdio.1LV.txt to cyfmac43012-sdio.txt  ,  If you can re-compile the fmac driver, you can enable the poll function to have a try.

                          in the sdio.c

                                    brcmf_sdio_probe_attach

                                              bus -> intr = false;

                                               bus -> poll = true;

                          default intr is enable, poll disabled.

                           

                          I just have a try about the nvram boardflags3 , it is ok to use internal or external for bringing up.

                          you can use internal LPO also to have a try.

                          0x44000100 .

                          • 10. Re: HT Avail timeout w/Murata 43012 1LV on Xilinx ZynqMP
                            JeHa_4771251

                            Hello,

                             

                            I had already updated the name of my nvram based on earlier failure and found the correct name in the kernel driver.

                             

                            I tried your latest suggestions but still no success.   The problem is that these changes, like the HOST_WAKE, are only valid after the chip has been successfully initialized.

                             

                            Do you know of a way to understand or debug why 'HT Avail' fails after loading the NVRAM?

                             

                            thanks,

                            jeff

                            • 11. Re: HT Avail timeout w/Murata 43012 1LV on Xilinx ZynqMP
                              ZhengbaoZ_96

                              Yes, I know the situation,  HT available status should be set to correct value if right firmware and nvram are loaded after interface up.

                              So would you please check :

                              1.  xtalfreq,  if it is 26M or 37.4M , and the value should be set to right position in NVram with corresponding value.

                              2.  if you are using module,  would you please check with module maker for a confirmed firmware + nvram for design ?

                              • 12. Re: HT Avail timeout w/Murata 43012 1LV on Xilinx ZynqMP
                                ZhengbaoZ_96

                                and better to lower the sdio speed for a try also.

                                • 13. Re: HT Avail timeout w/Murata 43012 1LV on Xilinx ZynqMP
                                  JeHa_4771251

                                  Sorry, I thought I had included the module, it is the  Murata LBEE59B1LV-278.

                                   

                                  1. I did try reducing the speed using max-frequency = <25000000>; in the device-tree and same result.

                                  2. the firmware I got from cypress-release-2020-06-25 has the same md5sum as the one from Murata's git repo

                                  3. I got the nvram file, cyfmac43012-sdio.1LV.txt, from Murata's git repo

                                  4. The nvram says the xtalfreq is 37.4.  I assume this is inside the module?

                                  5.  I did try two of our boards and they both fail the same way.

                                   

                                  This is the failing code.  Is the backplane clock dependent on the SD_CLK or the EXT_LPO ?

                                   

                                      /* Make sure backplane clock is on, needed to generate F2 interrupt */

                                      brcmf_sdio_clkctl(bus, CLK_AVAIL, false);

                                      if (bus->clkstate != CLK_AVAIL)

                                          goto release;

                                   

                                  I have attached the output of dmesg, I have TRACE, INFO and SDIO debug enabled.

                                  • 14. Re: HT Avail timeout w/Murata 43012 1LV on Xilinx ZynqMP
                                    JeHa_4771251

                                    I have another question.  I'm looking at the Figure 2 on page 5 of the CYW43012 datasheet.

                                     

                                    I just want to make sure that setting bit 27 to 1 in boardflags3 will force the use the the EXT_LPO.   Can the pmustatus register report if it sees the input signal on ext_lpo?

                                     

                                    Is the external LPO really needed or is it just for sleep?  If this signal was missing/bad would we get the HT Avail timeout?

                                     

                                    Sorry, that was more than one question but thank you very much for your help.

                                    jeff

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