6 Replies Latest reply on Sep 14, 2020 2:36 AM by RoAl_1242481

    Problem with CYCPROTO-062-4343W PDM Clock frequency




      I have a problem trying to get high frequencies using the PDM_PCM example. At standard frequencies, it works well, when I modify SAMPLE_RATE_HZ and DECIMATION_RATE I get the desired clock frequencies. The main problem is when I try to configure it with DECIMATION_RATE = 64 and SAMPLE_RATE_HZ 48000 to get a clock frequency of 3.072 MHz. When I analyze with an oscilloscope the signal clock output I only get 2.69MHz clock frequency with a duty cycle of 66.6%, which is quite strange.


      Any ideas of how can I get the correct clock frequency?