13 Replies Latest reply on Sep 29, 2020 11:40 PM by BragadeeshV_41

    Psoc 4100 s plus and SPI slave component 2.70

    ThBi_3905606

      I can not find the SPI slave compoent 2.70 or older in Psoc creator

       

      The only SPI slave available is the SCB one.

       

      I do not understand...

        • 1. Re: Psoc 4100 s plus and SPI slave component 2.70
          BragadeeshV_41

          Hi ThBi_3905606,

           

          SPI Slave component v2.70 is created using UDB resources. PSoC 4100 S plus device doesn't have a UDB resource in it. That is why you will not find this component for this device. PSoC 4100 S Plus device has a dedicated Serial Communication Block that can be configured as SPI interface.

           

          Are you looking for any feature that you can't find in the SCB component?

           

          Regards,

          Bragadeesh

          • 2. Re: Psoc 4100 s plus and SPI slave component 2.70
            ThBi_3905606

            Hello,

             

            I try to connect a Psoc 4200 L as a Master Bootloader Host  and a Psoc 4100 s plus as Slave via SPI,  and bootloading a new image for the slave.

             

            I use a SPIM 2.40 for the 4200 L (because all the API and code I found use a SPIM non- SCB) and a SCB SPI for the 4100 S plus

             

            But I have many trouble

             

            for instance, my MISO line has issue, and a message are not clean, the line stay high between two bytes/word

             

            Is it possible to had communication between SPIM and slave SCB SPI ?

            • 3. Re: Psoc 4100 s plus and SPI slave component 2.70
              BragadeeshV_41

              Hi ThBi_3905606,

               

              Yes, you can communicate between SPI (UDB) and SPI (SCB) component. Please refer the code examples SCB_SpiCommMaster and SCB_SpiCommSlave. (Open PSoC Creator , File > Code Example)

               

              If you do not want the SPI master to select the CS line between words, then give Transfer separation settings as separated. This will ensure that the CS line is de-asserted after every word (as configured in Rx/ Tx data bits settings).

               

              Regards,

              Bragadeesh

              • 4. Re: Psoc 4100 s plus and SPI slave component 2.70
                ThBi_3905606

                Hello,

                 

                I have issue, again,

                 

                Can I send the bootloadable file of my slave device directly with Psoc creator via SWD and after put a new bootloadable via bootloading ?

                 

                Because in my project, I put a bootloader in my slave device, an then a bootloadable but via SWD.

                Then a Master start bootloading for my second bootloadable.

                 

                If I put delay, my slave device seems to accept the bootloading, but in fact, after reset, the slave stay on the first bootloadable...

                • 5. Re: Psoc 4100 s plus and SPI slave component 2.70
                  BragadeeshV_41

                  Hi ThBi_3905606,

                   

                  Yes, the hex file of the bootloadable project will contain both the bootoader and the bootloadable code. Therefore when you flash the hex of bootloadable project, the bootloader code runs first (since a reset/ power cycle is done after programming is complete). It checks if there is a valid application (which is true in your case), then it switches control to the application (bootloadable). From your bootloadable, when the master/ host is ready with the new application, it can signal the application. Then the application can call the Bootloadable_Load() which will do a soft reset and enter bootloader mode. it should be noted the control stays with the bootloader only for Wait for command duration before switching  control back to the bootloadable. therefore the host should send the bootloader start command within this duration.

                   

                  In short, you can directly program the hex file of slave_bootloadable_1_c to your device.

                   

                  Regards,

                  Bragadeesh

                  • 6. Re: Psoc 4100 s plus and SPI slave component 2.70
                    ThBi_3905606

                    I though, the bootloader waits for ever after a bootloadable_load() command ?

                     

                    Again, my slave do not boot on the new application, very strange.

                     

                    there for; I notice that the data send by the Master/ Host is different to the string image

                     

                    may be I have an issue with my parse.c ?

                    • 7. Re: Psoc 4100 s plus and SPI slave component 2.70
                      BragadeeshV_41

                      Hi ThBi_3905606,

                       

                      Apologies for the confusion. You are right, when the Bootloadable_load() is called from the app, the bootloader waits forever to receive the new image.

                       

                      Can you please ensure that you are using the latest cybootloaderutils files from PSoC Creator 4.2 (or 4.3) installation directory?

                       

                      Regards,

                      Bragadeesh

                      • 8. Re: Psoc 4100 s plus and SPI slave component 2.70
                        BragadeeshV_41

                        Hi ThBi_3905606,

                         

                        Again, my slave do not boot on the new application, very strange.

                         

                        -> The default state of both the applications will be inactive. therefore you need to use the API CyBtldr_SetApplicationStatus(appID) to set the active state after the bootload operation is successful. This API should be called only after the application is successfully programmed and verified.  You can do the following to set which application should run (after both the images are loaded successfully).

                         

                        1. Send command 0x38 to enter the bootloader, ie CyBtldr_StartBootloadOperation()

                        2. Send command 0x36 to set the active application ID. ie CyBtldr_SetApplicationStatus(appID)

                        3. Send the exit_bootloader command (0x3B) to launch the application ,ie CyBtldr_EndBootloadOperation()

                         

                        If you want to launch the application straight away after bootloading, call the API CyBtldr_SetApplicationStatus(appID)  after CyBtldr_VerifyRow() and before CyBtldr_EndBootloadOperation(). I've attached a sample project to show the same. There are two switches, based on the switch app0 or app1 is loaded and launched.

                         

                        I've used SPI (SCB) as master for this project, you can use UDB component as well.

                         

                        Also, when you are loading the app0_bootloader hex file, ensure that you are loading the <app0_name>_1.hex into the flash using PSoC programmer. You can use the API Bootloader_Exit(0) to jump to this application from the bootloader project after successful programming.

                         

                        There is also an option to merge all the three projects into a single hex file and program using SWD lines. Later you can bootload the required image using the host device. Refer KBA Combine Dual-application Bootloadable Hex Files for Production Programming– KBA224390

                         

                        Regards,

                        Bragadeesh

                        • 9. Re: Psoc 4100 s plus and SPI slave component 2.70
                          ThBi_3905606

                          Hi Bragadeesh

                           

                          thank you for you example,

                           

                          I steel have issue, but now, I know where,

                           

                          for my first image, it is at CyBtldr_ProgramRow() fonction.

                          it fail at the first test.

                          than I change the unsigned char rowData[ ] in BootloadStringImage () fonction to 128 and now, it fail at

                          CyBtldr_ParseProgramRowCmdResult() fonction

                           

                          May be it's my stringimage that is not correct, I am lost.

                           

                          But the very stange thing is, that for the second image, it fail at the first test of the CyBtldr_ProgramRow() fonction.

                          • 10. Re: Psoc 4100 s plus and SPI slave component 2.70
                            ThBi_3905606

                            Hi,

                             

                            good news, since my last response I was able to bootloade succefully ! thank you very much !

                             

                            But I still have two questions :

                             

                            1 : I erase all the Uartputstring command, and I was not able to bootload. I add some cydelay() in place of the uart command and it's ok now strange behaviour ?

                             

                            2: may be there is a link to the first question, I use a logic analyser to see what happen on the SPI bus and I discover that I have a lot of peak on my CS line. It happen only with the 64 bytes messages, and my logic analyser made bad translation on the message with that peak (it miss some bits) Do you have some explantions ?

                             

                            How I can avoid those peak ?

                            • 11. Re: Psoc 4100 s plus and SPI slave component 2.70
                              BragadeeshV_41

                              ? Hi ThBi_3905606,

                               

                              Could you please share the waveform of the SPI transaction showing the issue? Are you referring to the CS line going high in between transactions? If yes, you can try the following:

                               

                              1. SPI HW FIFO depth is only 8 bytes. If the TX FIFO has no bytes to transfer it will deselect the chip select.In order to transfer 64 bytes, we use the software buffer and set TX and RX buffer size to 64 and the SPI interrupt takes care of data transfer. Make sure the SPI interrupt has the highest priority so that it is uninterrupted.

                               

                              2. If SPI interrupt can't be set to the highest priority, then you can use a software controlled SPI slave select. For example,

                               

                              SPI_SS0_Write(0); //Select SS0

                              Perform transaction

                              SPI_SS0_Write(1); //De-select SS0

                               

                              Regards,

                              Bragadeesh

                              • 12. Re: Psoc 4100 s plus and SPI slave component 2.70
                                ThBi_3905606

                                Sorry for the bad quality picture

                                 

                                You can see on the fourth line the Chip Select line, witch start at low at the start of that 64 bytes message.

                                 

                                And sometimes, randomly, the pin goes high.

                                 

                                Where can I find if the the SPI interrupt has the highest priority ?

                                • 13. Re: Psoc 4100 s plus and SPI slave component 2.70
                                  BragadeeshV_41

                                  Hi ThBi_3905606,

                                   

                                  Thanks for sharing the screenshot.

                                  Navigate to the interrupts tab in system wide resources. You should find the interrupt priority there. 0 is highest and 3 is lowest. default is 3


                                  You should not be seeing this issue if you use a software controlled CS pin as well.

                                   

                                  Regards,

                                  Bragadeesh