I believe the schematic in the parallel in/out section is the right one (PO is a mux selection between A0 or A1), because the TRM of PSoC5LP (which have the same UDB architecture) has consistent representation both in overview section and parallel in/out section. Below is a screenshot of the datapath overview from page 168 of PSoC5LP TRM: https://www.cypress.com/file/123561/download
and parallel in/out section in page 185 of PSoC5LP TRM
Cypress may have to update the PSoC6 TRM document regarding the datapath overview diagram.
I have a datapath that uses both PI and PO, and it works as intended (PO = A0 or A1 depending on what I select)