2 Replies Latest reply on Sep 17, 2020 12:32 PM by ChRe_4711096

    Confused by different schematics for datapath parallel in/out in architecture TRM

    ChRe_4711096

      The architecture TRM shows the ALU ASRC mux in two different ways, and they leave me a bit unsure about what I can expect. In the overview section we have this:

       

      Anmerkung 2020-09-07 095217.png

       

      The above schematic would indicate that whenever PI is selected by SRC A, PO = PI. However, in the parallel in/out section, this schematic is used:

       

      Anmerkung 2020-09-07 095124.png

       

      This indicates that I can use PI as input to the ALU, perform an operation on it, and store the result in A0 or A1 for parallel output. Which is right?

       

      My goal is to have the following instructions:

      • load A0 = D0; A1 = D1
      • PO = A0
      • PO = A1
      • PO = PI & A0