May I know which firmware version you are testing? Is it latest host SDK3.4 (https://www.cypress.com/documentation/software-and-drivers/ez-pd-host-software-development-kit )?
CCG3 firmware pre-write select logic in firmware example code:
1. VSYS is first priority power source of CCG3.
2. If VSYS is not available, the internal 20V regulator (on VBUS) will be enabled and VDDD switch will be switched to output of regulator.
3. If VSYS power is resume back, the internal 20V regulator (on VBUS) will be disabled and VDDD switch will be switched to VSYS.
As per the requirements of your description, the most important point to overcome the issue is: keep VDDD voltage higher than 2.75V.
So that, I could like to recommend:
1. Use VBUS power source to power CCG3 and do not switch if you can assure the VBUS will always existing.
2. Or use a larger Cap on VDDD (but the time from VSYS to VBUS on your case is a bit long.) for VDDD stand on above 2.75V.
I started with CYPD3125-40LQXI_notebook.cywrk version 3.3.1.
The latest host SDK3.4 version’s release notes indicate that there is nothing new for my CCG3 product.
Do I have software control over the switching between VSYS and VBUS to supply VDDD?
Another question: Is the internal switch that connects VSYS to VDDD bidirectional so that VDDD is forced to follow VSYS as VSYS decays? If that is the case then no amount of capacitance will keep VDDD from drooping.
CCG3 SDK have a function called vsys_is_present in the pdss_hal.c file which can be used by the customer to detect when VSYS gets removed. This is not interrupt based and has to be called periodically. You can use any desired voltage level, with the default being 3.2 V.
Once vsys falls below this level (the function returns false), do the following to turn on the LDO and turn-off the VSYS switch.
tmp = pd->vreg_vsys_ctrl;
tmp |= PDSS_VREG_VSYS_CTRL_VREG20_EN;
tmp &= ~(PDSS_VREG_VSYS_CTRL_ENABLE_VDDD_SWITCH |DSS_VREG_VSYS_CTRL_VREG20_ONOFF_CNTR_MASK);
pd->vreg_vsys_ctrl = tmp;