6 Replies Latest reply on Dec 13, 2016 6:51 AM by brainless

    SN8205 SDIO clock limit

    brainless

      Hi ghouse

      Is there any special reason to limit the SDIO clock in SN8205 to 24MHz (Wiced 2.4.1)?

      Is it possible to use 48MHz SDIO clock?

      According BCM43362 Data Sheet, it must support SDIO interface up to 50MHz.

      I tried to bypass the SDIO clock divider without success (the firmware can not be downloaded).

        • 1. Re: SN8205 SDIO clock limit
          ghouse

          Hi

           

          The SDIO interface on SN8205 is the BCM part interface but ST Micro controller interface (STM32F205). You can look at ST's data sheet for SDIO interface

          • 2. Re: SN8205 SDIO clock limit
            xlin_1779836

            Hi Brainless,

             

            SN8205 has no special limitation on the SDIO clock, and actually the SDIO clock is set to 48Mhz by default. The  PLL clock input  is 240MHz, PLL_Q=5, SDIO clock = 240/5 = 48Mhz.

             

            Hope it helps.

            Regards,

             

            Xinsi Lin

            • 3. Re: SN8205 SDIO clock limit
              brainless

              Thanks for the reply.

              SDIO clock is 48MHz, but prescaler (div by 2) is enabled by default, so actual clock is 24MHz.

              Please look at Wiced\Platform\common\ARM_Cortex_M3\STM32F2xx\SDIO\wwd_bus.c,

              function void host_platform_enable_high_speed_sdio( void );

              Prescaler is enabled.

              • 4. Re: SN8205 SDIO clock limit
                brainless

                Arrrgh.

                I found that there is very good reason to limit the SDIO clock output to 24MHz.

                STM32F205 Errata sheet state that SDIO can not work with prescaler disabled (hardware bug).

                There is a workaround (if USB and RNG are not used) to increase SDIO clock to 75MHz and leave the prescaler enabled.

                Actual SDIO clock will be 37.5MHz. To achieve this, clock settings(PLL) must be altered.

                Also, there is a disabled piece of code in wwd_bus_protocol.c file, which sets SDIO_SPEED_EHS bit in

                SDIOD_CCCR_SPEED_CONTROL register, to allow higher than 25MHz clock to be used with the BCM.

                I made everything and there was no problem with the communication at 37.5MHz SDIO clock, but

                I doesn't like this configuration, because I'm planning to use USB in the future and the System Clock must remain

                very low (75MHz).

                • 5. Re: SN8205 SDIO clock limit
                  ghouse

                  brainless

                  Since you found the answer, was there anything open on this.

                  • 6. Re: SN8205 SDIO clock limit
                    brainless

                    Hi ghouse, of course no.

                    1 of 1 people found this helpful