2 Replies Latest reply on Aug 31, 2020 2:08 AM by NoTa_4591161

    DMA cycles on PSoC6

    NoTa_4591161

      Hello,

       

      I am reading AN22875 ”DMA on PSoC 6 MCU”. So, I have a question about  "Elements of a Transfer" in section 10.1 and Table 1.

      Although it is written as 2 cycles in the explanation, it is 3 cycles in the table. Is this right?

       

      The explanation:

      A transfer can be split into multiple operations as shown in Table 1 with the corresponding cycles needed for their execution. Each transaction is initiated by a trigger, which goes through trigger synchronization circuit and takes up two cycles. These two cycles will be consumed whenever there is a trigger event being used.

       

      Table 1:

      OperationCycles (Slow Clock Cycles)
      Trigger Synchronization and Priority decoding3
      Start state machine and load channel config3
      Load descriptors

      4 for single transfer

      5 for 1D transfer

      6 for 2D transfer

      Load next pointer 1

      1
      Moving data from source to destination3

       

      Thanks,

      Kenshow