2 Replies Latest reply on Aug 31, 2020 2:28 AM by EktaN_26

    Is a datapath with parallel input compared to zero more efficient than a 4-input OR gate?

    ChRe_4711096

      I'm looking for ways to ease the chip from some combinatorial logic. I have 4 instances of a component that has a 4-input OR gate, and I'm tempted to remove that OR gate by moving it into a datapath. I'd use parallel in, and use the all-zero detector (inverted) to see if any bit is set - if that is feasible at all. Would that use less PLD resources than a 4-input OR gate? the number of signals (4 in, 1 out) is the same, but does it "free the way" for other parts of a larger design?

       

      Also, could this be combined with a memory-to-hardware latch (D register to accumulator to parallel out)?