1. What is the size/amount of data that you want to transfer?
2. How are you triggering the DMA component?
If possible, can you please attach the project for us to test at our side?
I've never used the EMIF component. But here goes my "2 cents"...
I noticed that you have the BUS_CLK set to Fbus_clock = 60MHz. At this bus clock a write cycle should complete in 100ns. This results in a max Write transfer of 10MBps. With the BUS_CLK at 60MHz the required 4 BUS_CLKs between EMIF accesses are satisfied.
However, Fbus_clock = 60 MHz nearly doubles the maximum allowed of 33 MHz.
Theoretically the EMIF component should have complained about the excessive BUS_CLK frequency.
If you back down Fbus_clock = 33MHz. then a write cycle is 166.67 ns => 6 MBps. The required 4 EMIF cycles at this BUS_CLK allows a EMIF transfer rate at 7.5 MBps.
Try lowering the BUS_CLK to 30 MHz. Maybe there is an issue with the way the EMIF component is written.
I think that the right way will be to DMA data to the RAM (1024 bytes), and then to save it to external memory.
I changed BUS_CLK to 30MHz, but the memory access speed did not change.
I Try DMA transfer the data to RAM and then saving it to external memory.