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You could do a WORD to WORD transfer to 2x 16-bit datapath. You need to place these two datapaths adjacent to each other.
One of them will store the 16-bit ADC result. The other 16-bit will store the two bits.
If you are tight in number of datapaths, then you could place the 32-bit result in RAM first. Then trigger another DMA to parse the results. You can copy the limit result in a control register.
I'm not exactly tight in number of datapaths, but routing resources. One 16-bit dp was already troublesome, and two would probably not work at all. I tried the ADC -> word to 32-bit memory -> 2 bytes to 8-bit dp approach and it worked with one transfer with two descriptors. That's probably a reasonably simple and efficient approach. The test code - without any ADC involved, but showing the DMA setup - is attached.
Regarding your suggestion to copy the limit result to a control register - it's not that simple since I need to demux the limit result to 1 of 4 different destinations, based on input previously received from those 4 destinations. It's turning out to be very hard to transform a naive schematic based approach to something that is easier to route with good use of datapaths, especially when used in parallel in/out mode. Outlining the whole task and problem here in the community feels like a huge effort with little hope of success.