It seems that the load capacitance on the SPI bus increased by increasing the number of devices connected on the bus.
Please reduce the SPI clock frequency. All devices can be accessed if the load capacitance is the root cause.
I tried reducing the clock speed and still no luck. Any other suggestions?
On Wed, Aug 19, 2020 at 11:55 PM Noriaki Tanaka <
Then, please check the SPI bus with an oscilloscope.
* Is only one CS# asserted from three or four devices?
If more than one device is selected by CS#, SO has unexpected signal.
* Does SCLK have eight pulses per a byte?
PSoC should be the only one driver for SCLK signal.
* Does SI have expected bit pattern?
SI is also driven by PSoC only.