Error when trying to assign .po() for a datapath

[ChRe_4711096]

I'm trying to make a CPU-writable 9-bit latch that forwards from D0 and D1 to parallel out and (as 9th bit) A1==0, when INSTR_ADDR[0] == 1. The instruction at address 1 simply loads A0 from D0 and A1 from D1. A0 should be the parallel output, and is split into single bits (Ap, Ac, Bp, Bc, Cp, Cc, Ain0, Ain1).

I've pre-configured my datapath using the UDB editor, copied the generated verilog code to a new file, and modified it to connect the datapath's parallel output to a module output - see attached file.

However, I'm getting the following error:

Pin guidance unavailable: 'po' not a port of module 'cy_psoc3_dp8'

How do I connect to a datapath's parallel out? The Appendix of AN81256 wasn't helpful either. The examples say "parallel in" or "parallel out", but they don't actually connect anything using pi() and po().

[RodolfoGL · Accepted solution]

The cy_psoc3_dp8 is a wrapper to the cy_psoc3_dp. It hides some of the inputs and outputs of the base datapath module, including the pi() and po().

That means you need to use the cy_psoc3_dp module to access the parallel signals. You can use the Datapath Configuration Tool to create the template for you.

PSoC Creator > Tools > Datapath Config Tool.

In the tool, go to:

Edit > New Datapath..

Select Instance Type = cy_psoc3_dp.

[ChRe_4711096]

Oooh that's better. I've created a symbol for it, but now all output pins are reported as floating. Why is that? As far as I can tell everything is fine.

[RodolfoGL]

The problem is this line:

assign A0 = ({Ap, Ac, Bp, Bc, Cp, Cc, Ain1, Ain0});

It should assign the opposite:

assign Ain0 = A0[0];

assign Ain1 = A0[1];

assign Cc = A0[2];

...