2 Replies Latest reply on Aug 19, 2020 12:30 AM by ChRe_4711096

    Confused by missing (?) warning about max UDB clock speed

    ChRe_4711096

      In the attached project I've set clk_peri to 72 MHz and my (UDB/datapath based) peripherals are clocked at 36 MHz (clk_udb), which is 72/2 MHz. I did this because 72 MHz or similarly high clock speed resulted in an error because clock_udb may not exceed clk_peri/2.

       

      However, this error does NOT appear when I set clk_udb clock to 48 MHz, which is clearly faster than clk_peri/2. Why does this error message not appear then? It comes back when I increase from 48 to 56 MHz.

        • 1. Re: Confused by missing (?) warning about max UDB clock speed
          EktaN_26

          Hello ChRe_4711096,

           

          UDB can be clocked at a maximum of 100Mhz.

          Also, by default the clk_peri divider is set to 2. In order to clock the UDB component to upto 100 MHz kindly make the following changes in the clock settings:

           

          In the Configure Systems Clock dialogue box:

          1.Under the FLL/PLL tab set the PLL to a frequency of 100Mhz.

           

          2. Under the High Frequency Clocks tab set the clk_peri divider to 1.

           

          3. Now in the top design set the clock to a frequency of 56 Mhz and the project should build successfully.

           

          Please refer to the following Forum post which mentions in detail how to make the clock settings to clock a upto UDB component: Re: How to clock a UDB component at 100MHz

          I have modified the project to set the clk to 56Mhz and attached below.

          Please let me know if this resolves the issue at your end.

           

          Best Regards

          Ekta

          • 2. Re: Confused by missing (?) warning about max UDB clock speed
            ChRe_4711096

            I looked into my top level design again and indeed the error disappeared when using the existing Clk_Peri (72 MHz) instead of a new clock.

             

            Side note: The reason I won't go up to 100 MHz is that the ADC is supposed to run at 18 MHz, and 72 is the highest multiple of that while still allowing the M4F to run at more than 100 MHz (2*72 MHz = 144 MHz).

             

            There's still a setup time violation going on, but that will go into a different question.