UDB can be clocked at a maximum of 100Mhz.
Also, by default the clk_peri divider is set to 2. In order to clock the UDB component to upto 100 MHz kindly make the following changes in the clock settings:
In the Configure Systems Clock dialogue box:
1.Under the FLL/PLL tab set the PLL to a frequency of 100Mhz.
2. Under the High Frequency Clocks tab set the clk_peri divider to 1.
3. Now in the top design set the clock to a frequency of 56 Mhz and the project should build successfully.
Please refer to the following Forum post which mentions in detail how to make the clock settings to clock a upto UDB component: Re: How to clock a UDB component at 100MHz
I have modified the project to set the clk to 56Mhz and attached below.
Please let me know if this resolves the issue at your end.
I looked into my top level design again and indeed the error disappeared when using the existing Clk_Peri (72 MHz) instead of a new clock.
Side note: The reason I won't go up to 100 MHz is that the ADC is supposed to run at 18 MHz, and 72 is the highest multiple of that while still allowing the M4F to run at more than 100 MHz (2*72 MHz = 144 MHz).
There's still a setup time violation going on, but that will go into a different question.