Query regarding QDR II+ chip data read write failure.
QDR II+ Interface: Two CY7C2663KV18-550BZI (SRAM# 1 & SRAM#2) are connected with Kintex 7 FPGA part# XC7K325T-1FF900I in our board as shown in datasheet (Figure 2. Application Example)
We have two similar boards.
Issue:- QDR II+ Counter data write/read and QDR II+ Pattern (A55AA55A) data write/read fails (random failure) in board 1. While the same test run without fail in board2.
Attached the QDR II+ Counter data write/read testcase fail log in attachment1 and QDR II+ Pattern (A55AA55A) data write/read testcase fail log in attachment2
From the log in attachment1, it is observed that the Counter data write/read fails only at LSB C address.
We are suspecting the failure is due to QDR II+ SRAM# 1 IC CY7C2663KV18-550BZI chip.
Waveform for QDR Data out (channel 2) signals Q, Q, Q, Q, Q & Q are probed with respect to Clock K (Ball B6 in channel 4) and Read Port Select RPS# (Ball A8 in channel 3) is attached for reference.
During failure, it is also observed that the RPS# is not asserted. The power supply rail (1.8V) rise time is around 136uS.
IC Top Marking : CY7C2663KV18
Batch Code: 1825
It would be helpful if you provide solution for this.