Can you please elaborate on your target application so that i can provide a suitable firmware example suggestion?
Also, the cyfxmscdemo example is used to emulate a Mass Storage Class functionality on the FX3 SuperSpeed Explorer Kit by allocating 32KB of the available RAM space.
To answer to your queries:
1.) It is not possible to create another channel between CPU and P-port because both the CY_U3P_CPU_SOCKET_CONS and CY_U3P_CPU_SOCKET_PROD are already being used in channel creation of the msc implementation.
2.) Yes, your understanding of the API is correct and the register reads and writes will be slower compared to dma mode.
I have CYUSB3KIT-003 and want to connect this board to an FPGA board using CYUSB3ACC-005.
Let say, instead of 32KB of the RAM space of FX3, I want to use FPGA BRAM for mass storage read/write space.
In the cyfxmscdemo, there is no gpif interface.
1) How should I connect FX3 to FPGA and still use the mass storage functionality?
As far as I see, there is only one (AN65974) example design that connects FX3 to FPGA using dma and gpif, but this only transfers raw usb data?
Firstly, I thought I could create another dma channel between cpu port to p-port, but as you confirmed, it is already being used.
2) Secondly, if I use CyU3pGpifWriteDataWords()-CyU3pGpifReadDataWords() functions in cyfcmscdemo, how will the read/write performance be affected? Will it still sustain usb3.0 performance?
3) If register read/write is the only option to read/write data to gpif, how should the gpif state machine be? Can the master state machine in AN87216 be used by only changing IN_DATA and DR_DATA Data Sink and DataSource from Socket to Register?
4) Is there any design alternative or advice ?
To connect FX3 as a master to FPGA as a slave and still use the mass storage functionality, you would need to integrate the state machine provided with the AN87216 to the cyfxmscdemo example firmware and port the related functionality from the cyfxbulklpauto.c file of the AN87216 firmware so that the cyfxmscdemo and state machine are in sync.
In the cyfxmscdemo.c file, you would need to change the MANUAL_IN and MANUAL_OUT channels between UIB and CPU to either AUTO or MANUAL channels and between UIB and PIB such that the GPIF interface can be utilized to transfer data to the FPGA, while the FX3 still handles the mass storage functionality related stuff.
You can take the channel creation in the cyfxbulklpauto.c as a reference and change the channel creation in cyfxmscdemo.c file (as shown in the attached image).
2.) If you use CyU3pGpifWriteDataWords()-CyU3pGpifReadDataWords(), it is not possible to achieve USB 3.0 performance.
3.) You can use the state machine provided with AN87216 and integrate the state machine to the cyfxmscdemo example firmware as mentioned above.
channel_creation.jpg 146.2 K
I did the following major changes:
1) I changed the DMA channels as you showed in the channel_creation.jpg
2) I initialized the p-port block ( same with AN87216-AutoMaster-cyfxbulklpauto.c)
3) I set the sys-clk ( same with AN87216-AutoMaster-cyfxbulklpauto.c)
4) My gpif configuration is the same with AN87216 master_read_write_sync.cyfx
5) I set CyU3GpifSocketConfigure(0, CY_U3P_PIB_SOCKET_0, 4, CyFalse, 1) // producer socket
CyU3GpifSocketConfigure(1, CY_U3P_PIB_SOCKET_1, 4, CyFalse, 1) // consumer socket
When I debug the signals from FPGA side, I perfectly observe SLCS,SLOE,SLRD, PCLK signals as expected. That is, FX3 reads data from FPGA.
However, FX3 does not send data to FPGA. SLWR signal is never asserted.
I think GPIF state machine does not jump to WR_FLAG state.
I drive the FLAGA, FLAGB, FLAGC correctly.
I think DMA_RDY_TH1 is not asserted. How can I debug or print this?
What could be the possible reason?
Could you reproduce the same case on your side?
Apologies for the delay.
Please try the following:
1.) uint8_t SMState = 0; (declare as either a local or a global variable)
2.) In the for ( ; ; ) loop in CyFxMscAppHandleMscTask(), do the following:
CyU3PDebugPrint (4, "\n\rAplnStop:SMState = 0x%x",SMState);
Please share the UART debug logs when you try to do the write action.
Also, can you please let me know what is the data size that you are writing to FX3?
1) When I debug the GpifStateMachine as you stated, UART prints continously
AppInStop:SMState = 0x01 // (RD_WR_IDLE)
AppInStop:SMState = 0x03 // (DR_ADDR ) when FLAGA is asserted
Interesting thing is, uart does not print other read states, although I catch SLCS,SLOE,SLRD, PCLK signals correctly from FPGA. ?
2) Since I use cyfxmscdemo, as soon as FX3 connects to the PC, it asks to format disk. PC sends (Read10) command and FX3 calls
I think CyU3PDmaChannelSetupSendBuffer(&glChHandleBulkLpPtoU, &dmaBuf); triggers GpifReadStates. Is it right?
When I click format disk (still 32 KB ram space of FX3), PC sends (Write10)command, FX3 calls CyFxMscAppInReceiveUsbData().
CyU3PDmaChannelSetupSendBuffer(&glChHandleBulkLpUtoP, &dmaBuf) does not trigger GpifWriteStates.
3) I also added CYU3PGetUsbSpeed() and set the GPIFInitDataCounters() accordingly before DMA channel creation(as in cyfxbulklpauto.c)
and CYU3PGetUsbSpeed() returns 0. What could be the possible reason? Is there any additional driver needed?
1)Please try the following:
a.) Add two global variables, uint8_t prod; uint8_t cons; in the firmware.
b.) For the MANUAL_IN channel, change the notification as below:-
dmaConfig.notification = CY_U3P_DMA_CB_RECV_CPLT | CY_U3P_DMA_CB_PROD_EVENT;
For MANUAL_OUT channel, change the notification as below:-
dmaConfig.notification = CY_U3P_DMA_CB_SEND_CPLT | CY_U3P_DMA_CB_CONS_EVENT;
c.) In the CyFxMscApplnDmaCb(), add two more cases for PROD and CONS events and increment the prod in PROD event case and cons in CONS event case as below:-
d.) In the for ( ; ; ) loop, print the prod and cons count as follows:
CyU3PDebugPrint ( "Prod = %d Cons = %d", prod, cons );
Please add these in the firmware and share the UART prints with me.
2) I will need to confirm this and will let you know.
0x00 corresponds to USB device not connected.
This is not expected.
Please share how you are calling the CYU3PGetUsbSpeed() API.