1) Is it correct that instead of using a Xilinx FPGA, you can also use an Altera FPGA when you want to use the FX3's FPGA configure feature discussed in AN84868 ?
Yes, Altera Cyclone FPGA can be programmed using the configuration from AN84868.
2) We read somewhere (can't find the exact source at the moment) that when you use the FX3's SPI interface to configure an FPGA, you can no longer use the GPIF II's bus with 32 bits and are forced to use it in 16 bits. Is this correct? We truly hope this is incorrect or only applies in certain situations since we really want to use the full 32 bits AND the FPGA configure option.
When FX3 GPIF is configured for 32-bit data, the SPI interface will not be available. Please refer to Table 7. CYUSB3012 and CYUSB3014 Pin List in the FX3 datasheet.
In the Application note AN84868, the GPIF interface is initially set to 16-bit, when the FPGA is being configured.
Once the FPGA configuration is complete, the interface is switched to 32-bit wide for the application requirement.
Only when using the SPI interface, 32-bit GPIF data bus cannot be used.
3) What is the best (or easiest) way to access (read/write) control/status registers in the FPGA? We couldn't find any examples for this in Cypress's documentation. Is this normally done by creating additional (DMA) threads for reading/writing FPGA's registers (with extra control signals)? Or is it easier to eg. use I2C for this and only use the GPIF II's bus for data transfers to the host?
In an application scenario when sending or receiving data from the FPGA, yes, you can use both the ways to access the registers of the FPGA, provided you have the provision to do it.
Using I2C for accessing registers and using GPIF lines only for sending/receiving data is an ideal case.