In the PSoC6 Programming Specifications (Rev L), Section 5, "Step 1.A Acquire Chip" pseudocode there is a step to set the TEST_MODE bit in the TST_MODE_SRSS register.
// Enter CPU into Test Mode // Set TEST_MODE bit in TST_MODE SRSS register WriteIO (SRSS_TST_MODE, SRSS_TST_MODE_TEST_MODE_MSK);
Later this bit is checked:
// Check TEST_MODE bit is set ReadIO (SRSS_TST_MODE, OUT dataOut); if ((dataOut & SRSS_TST_MODE_TEST_MODE_MSK) == 0) return FAIL;
I can find no details about where this SRSS_TST_MODE (or TST_MODE_SRSS) register is located, or how to construct the SRSS_TST_MODE_TEST_MODE_MSK mask.
The only lead I've found is that the PSoC4 had SRSS (System Resource) registers, it appears.
I have didn't see anything related in the PSoC 63 Architecture TRM, nor in the Register TRM. Searching the broader internet, and ARM resources have not helped so far.