1 Reply Latest reply on Aug 6, 2020 10:12 AM by WaMa_286156

    PSOC 5LP Shift Register Ugh!

    WaMa_286156

      I want to shift *a lot* of bits out in a steady stream (without gaps between the bits).

       

      So I set up a Shift Register for a test.  I set it up to be 32 bits. I sent the output into a pulse convertor to get a 2us pulse out no matter the width of the input pulse.

       

      I then  ran the DMA AN52705 project and realized that was not what I wanted.  (too long between bits, plus some suspicion of when the bits went out)

       

      I then set up a single shift register for 32 bits and wrote 0x55555555L into it.  I got 16 pulses.  good.

       

      So then I tried reading the Fifo, which the *Documentation* says is there.

       

      After much experimentation, the Shift Register Documentation is wrong.   You do not get an input fifo unless you use the Load signal.  If you use the Load signal, you must programmatically control the loading of the Shift Status Register when the shift has ended.  There are no indications the shift has ended from the component, as the "Store" signal must be controlled programmatically also.

       

      About the only way to really use the component is to make sure you don't select the load and store signals, and put a lot of hardware or firmware around the shift component to provide you with an indication of when the shift has ended so you can either generate a load pulse or programmatically load the shift register.

       

      Has anyone done this?