1 Reply Latest reply on Aug 5, 2020 2:48 AM by YatheeshK_36

    Does the FX2LP Send and Receive LSB First in FIFO And in SLAVE Mode?

    FrZa_2625781

      Hi,

       

      In the

       

      001-13670_EZ-USB_Technical_Reference_Manual

       

      under

       

      10.2.8 Byte Order for 16 Bit GPIF Transactions

       

      it states that

       

      "Data is sent over USB in packets of 8-bit bytes, not 16-bit words. When the FIFO Data bus is 16 bits wide, the first byte in every pair sent over USB is transferred over FD[7:0] and the second byte is transferred over FD[15:8]."

       

      I want to use a 16 bit wide data bus (D[15:0]) in order to transfer 32 bit data, where the first 16 bits put on the bus at D[15:0] are the data bits [31:16] beginning with the MSB and the second 16 bit are the data bits [15:0] ending with the LSB.

       

      As the USB sends 8 bit data, I would need to have the sequence that is sent to be data bits [31:24], then data bits [23:16], then data bits [15:8] and then data bits [7:0].

       

      If the first byte sent over USB is transferred over FD[7:0] and the second byte is transferred over FD[15:8], does this mean that I have to wire the MSB of the 16 bit wide data bus (D[15:8]) to FD[7:0] and the LSB of the 16 bit wide data bus (D[7:0]) to FD[15:8] ?

       

      The above quote is about the GPIF. Does this byte order also apply to the SLAVE FIFO? And does this apply to both IN and OUT transactions?

       

      Thanks,

      Frank

        • 1. Re: Does the FX2LP Send and Receive LSB First in FIFO And in SLAVE Mode?
          YatheeshK_36

          Hello Frank,

           

          When connecting between FX2LP configured as Master and Slave, the Data lines of master should be connected to the corresponding data lines of the slave, i.e. D0 of master should be connected to D0 of slave, D1 of master to D1 of slave and so on.

           

          FX2LP uses FIFOs for transferring data between the USB side and its peripherals. The data stored in the first byte of the FIFO buffer (FIFOBUF[0]) will be pushed out first on to the data lines in both GPIF Master and Slave FIFO configuration.

          Similarly when reading the data, the first byte that is received on the data bus will be copied to FIFOBUF[0] and so on.

           

          For your understanding, I have used the GPIF master example and assigned each byte of the FIFO buffer with the corresponding index value.

           

          The GPIF side data captured using Saleae logic analyzer is as below.

           

           

          The above capture is for asynchronous data transfer. So, the SLWR negative edge is considered.

          I have also attached the logic capture file to this response.

           

          Thanks,

          Yatheesh