When connecting between FX2LP configured as Master and Slave, the Data lines of master should be connected to the corresponding data lines of the slave, i.e. D0 of master should be connected to D0 of slave, D1 of master to D1 of slave and so on.
FX2LP uses FIFOs for transferring data between the USB side and its peripherals. The data stored in the first byte of the FIFO buffer (FIFOBUF) will be pushed out first on to the data lines in both GPIF Master and Slave FIFO configuration.
Similarly when reading the data, the first byte that is received on the data bus will be copied to FIFOBUF and so on.
For your understanding, I have used the GPIF master example and assigned each byte of the FIFO buffer with the corresponding index value.
The GPIF side data captured using Saleae logic analyzer is as below.
The above capture is for asynchronous data transfer. So, the SLWR negative edge is considered.
I have also attached the logic capture file to this response.