One doubt regarding the design, why the descriptors are chained to each other ? How often the trigger signal (EOS out) is generated?
The descriptors are chained because they transfer both a timestamp and an ADC sample. Two of these tuples are used to calculate the time at which the ADC input crossed zero. EOS out is triggered at roughly 360 90 kHz, and I might try to double that to 720 180 kHz. (Sorry for the previous values - they were the sum for 4 ESC components)
I've attached an 8-bit demo of the UDB I'll use to extract the ADC sample sign and generate separate triggers based on that. It also allows to set a threshold around zero, for blanking out noise.
Hi ChRe_4711096 ,
To answer your initial question about "cascading the DMAs" please find the attached project in which I have cascaded two DMA components. The input trigger to the first DMA (DMA_1) is given using the TCPWM based counter.
Please check if it is working at your side and update me.