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If using the external clock, you need to watch out the oversampling factor. If set to 16, it should be 160 kHz.
> If using the external clock, you need to watch out the oversampling factor. If set to 16, it should be 160 kHz.
Thank you! I was not paying attention to it. >_<
The I2C specification document is provided by NXP and the document number is UM10204.
In the specification there is no specification regarding the bus line length, but many timings are specified.
When the bus line becomes longer, the bus line acts as a resistor. If the bus line is longer ten times, the resistor becomes ten times bigger, and the rising/falling time is also ten times longer. This is why the maximum clock is lower when the bus line longer.
To reduce the rising/falling time, it will be effective to reduce the bus line resistance. This requires thick wire.
Please note that the specification document has a recommendation for a long bus line as follows.