7 Replies Latest reply on Aug 4, 2020 5:49 AM by BragadeeshV_41

    Serial NVRAM sharing SPI

    LeEs_793571

      Hi,

       

      I have a project that has a W5500 and an SPI FRAM sharing the same SPI bus. All appears to be fine, but I haven't really tested the combination in anger and one thing has just struck me.

       

      The W5500 uses SS0 from the SPI component (which is set by the SpiSetActiveSlaveSelect() call) and the FRAM is using the Serial NVRAM component with it's own CS line.

       

      Looking at the code in the Serial NVRAM component I can't see it doing anything to "unselect" the SPI SS0 line, therefore my assumption is that this will also be active during the NVRAM operations (since it will be pulled low by the SPI operation) and therefore any FRAM operations may well have unexpected side effects on the W5500?

       

      If I'm correct it's really not a problem since I can easily wrap the relatively infrequent FRAM calls with SetActiveSlaveSelect() calls to a non-used SS line or disconnect SS0 using the HSIOM, but this does seem like a fairly obvious omission from the code (or at least the Datasheet) ???

       

      Does anyone know if my assumption is correct?

       

      Thanks,

       

      Lee.

        • 1. Re: Serial NVRAM sharing SPI
          BragadeeshV_41

          Hi LeEs_793571,

           

          How can the two SPI slaves shares the same bus when they are controlled by two different master (within PSoC)? Could you please share a snap shot of your connection (schematic/ drawn representation),  Top design of your psoc creator project and the Pin assignments made. Are the two pins of these components (SPI SCB master and SPI NVRAM) shorted externally?

           

          Please help us understand your question better.

           

          Regards,

          Bragadeesh

          • 2. Re: Serial NVRAM sharing SPI
            LeEs_793571

            Hi Bragadeesh,

             

            I'm not sure why you assume there are two different masters?  The Serial_NVRAM component uses an existing SPI component to communicate (and only has it's own SS line, or CS in this case.)

             

            So I have one SPI (Master) component which has a SS0 line which is the CS for the W5500, and then I have a Serial_NVRAM component that uses the same SPI (Master) component to communicate, but with it's own SS line.

             

            (I actually don't have enough pins to add another SPI component, but that's unnecessary anyway since it's all working, I'm just trying to understand the implications of my FRAM access impacting the W5500, so it's a theoretical question and doesn't really need me to post a design.)

             

            Lee.

            • 3. Re: Serial NVRAM sharing SPI
              BragadeeshV_41

              Hi LeEs_793571,

               

              Thanks for clarifying. Serial_NVRAM component uses it's own set of SPI CS lines (not part of HW block). It selects and deselects the CS lines in firmware. If you are using Serial_NVRAM component, the no of SS option in SPI master component should be set to 0. This ensures that when a SPI transaction happens using Serial_NVRAM component, the SS line is not de-asserted. But if this option is set to 1 or more, then transactions in NVRAM component will assert the SS line associated with the SPI hardware.

               

              For your application you can do the following

              1. Set the No of SS lines to 0. When using for W5500, use the API, SCB_SpiSetActiveSlaveSelect() to set the correct SS line. Then use HSIOM to connect the pin to the SPI HW block. You need to disconnect the SS line from the pin(SS of W5500) using HSIOM before performing NVRAM transactions. Otherwise the SPI hardware will toggle this pin.

               

              or

               

              2.  Set the No of SS lines to 0. Instead of making a HSIOM connection to the hardware block, you can simply toggle the pin (SS of W5500) in firmware just like how NVRAM does it.

               

              Regards,

              Bragadeesh

              • 4. Re: Serial NVRAM sharing SPI
                LeEs_793571

                Hi Bragadeesh,

                 

                Actually, as per my first message, I think the better option would be to use SCB_SpiSetActiveSlaveSelect() to something that isn't used (1, 2, or 3 in my case) during the FRAM operations as I suspect it will be quicker, simpler, and more easily understood than messing with the HSIOM (which I also mentioned in my first post!)

                 

                I was hoping that this might trigger someone from Cypress who could actually get the datasheet updated appropriately!

                 

                Thanks,

                 

                Lee.

                • 5. Re: Serial NVRAM sharing SPI
                  BragadeeshV_41

                  Hi LeEs_793571,

                   

                  Yes, that can be done. However, it will lead to unnecessary GPIO wastage for this purpose and might not be an option that is suitable for everyone. NVRAM component was designed to interface with multiple memory products with a single SPI component. It is recommended to use NVRAM and SPI component (your use case) together only after understanding the effects we discussed here. The NVRAM component comes with a note that SPI component should have the no of slaves as "0" indicating that it is not suited for normal SPI operation other than memory interfaces.

                   

                  Having said that, I will raise an internal request to update the document or create a Knowledge Based Article (KBA), highlighting the effects of sharing the same bus for SPI component and NVRAM component.

                   

                  Best regards

                  Bragadeesh

                  • 6. Re: Serial NVRAM sharing SPI
                    LeEs_793571

                    Hi Bragadeesh,

                     

                    I am going to have to disagree with you on two counts...

                     

                    1. It doesn't need to waste a GPIO .. SS1 (or 2, or 3) doesn't actually need to be connected to a physical pin at all. All it's actually achieving is not using SS0. I would leave the slave count as 1 in the component, not add an additional one.

                    2. The datasheet does not say to set the number of slaves to zero, in fact it says "Set the Number of SS to 0 when the SPI is not planned for other purposes.", and then later on it says "Note The SPI Master Component has its own SS pins, which are not used in the Serial

                    NVRAM Component. These SS pins can be disabled if they are not used for other purposes."

                     

                    Surely the whole point of the Serial_NVRAM component using a separate SPI component is to share it! Otherwise you would have just built the Serial_NVRAM component with SPI embedded ... which of course would be a criminal misuse of pins and SCB's.

                     

                    Thanks for raised the request to document this ... I do think it's quite important.

                     

                    Lee.

                    • 7. Re: Serial NVRAM sharing SPI
                      BragadeeshV_41

                      Hi LeEs_793571,

                       

                      1. I had assumed you connected the HW signal to the corresponding pin. Otherwise, agreed it doesn't waste the pin, it is only the hardware signal that is toggled.

                      2. I understand. We need to add a note mentioning these implications when using SPI component for other purposes.

                       

                      Thank you for pointing this out! We will work towards making these points clear in the datasheet

                       

                      Regards,

                      Bragadeesh