3 Replies Latest reply on Aug 2, 2020 11:38 PM by SudheeshK_26

    HyperRAM read operation

    SaK_4745916

      Hi ,

       

       

      We are integrating microblaze (from xilinx) with hyperbus IP. And we are using AXI4. We are facing issue in HyperRAM simulation.

      While trying to simulate using the frequency of 60Mhz , we have provided 6 cycles of latency in the test bench (as per the data sheet) .

      The attached screenshot "HyperRAM_Read_60M_6_Cycles_Part1.PNG" and "HyperRAM_Read_60M_6_Cycles_Part2.PNG" show the same .


       

      The AXI is configured to read one 32 bit word ,and the data of 33441122 is being read properly in AXI the same is observed in the screenshot "HyperRAM_Read_60M_6_Cycles_AXI.PNG" ,


       

      According to our understanding , the chip select should have got deasserted once these 4 bytes are read on the DQ line. But chip select still continues to be valid and CK_P and CK_N lines are providing valid clocks to the hyperRAM device and the hyperRAM would keep sending the next bytes . But these cannot be read on AXI as it is configured for 4 bytes(1 32 bit word) .


       

      Can u please provide inputs on why the cypress driver is sending extra clock cycles and also maintaining the chip select valid for longer duration ?
        • 1. Re: HyperRAM read operation
          SudheeshK_26

          Hello,

           

          It is an expected behavior of the HyperBus controller. The controller de-asserts the CS and stops CK when it determines that there is no more read request. There can be time lag between last read and the determination, and some redundant CK cycles are seen during that period. I hope this information answers your query. Please feel free to ask if you have any related queries.

           

          Thanks and Regards,

          Sudheesh

          • 2. Re: HyperRAM read operation
            SaK_4745916

            In the hardware if the memory controller sends extra clock cycles then the memory device will read extra bytes. This data will be discarded by the memory controller. Will it not introduce loss of data in the hardware?

            • 3. Re: HyperRAM read operation
              SudheeshK_26

              Hello,

               

              I am not clear about your last query regarding "loss of data in hardware". Are you talking about data loss from HyperRAM device because of the extra clock cycles? Please clarify.

               

              As we already discussed, HyperRAM will send data out as long as it receives clock signal. A read operation will not change data already stored inside HyperRAM irrespective of whether the host reads the data from HyperRAM or not. Only a power cycle or a write operation can change data stored inside HyperRAM device.

               

              Thanks and Regards,

              Sudheesh