1 2 Previous Next 15 Replies Latest reply on Aug 18, 2020 11:15 AM by YatheeshK_36

    FX2 streaming and GPIF

    raus_1269711

      Does GPIF work for streaming applications too?

       

      Also, I have tried to add a GPIF file to the standard bulkloop program given in the development kit.

      I get the following message when I build the target.

      *** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS

          SEGMENT: ?PR?GPIFINIT?GPIF

       

      Can any one help me as what to do ?

      Thanks,

        • 1. Re: FX2 streaming and GPIF
          YatheeshK_36

          Hello,

           

          GPIF designer is used when then FX2LP is configured to function as a GPIF master.

           

          Yes, you can use the GPIF designer for other firmware from the FX2LP DVK, but with a lot of changes in the firmware.

           

          I would recommend you to go through AN66806 Getting Started with EZ-USB® FX2LP™ GPIF, It has a firmware included with it and details the steps to implement GPIF master on FX2LP.

           

           

          If you need to add the GPIF functionality to the bulkloop firmware (or any other similar firmware), follow the below procedure:

           

          1. Create the GPIF designer project with necessary interface signals and the required timing diagram.

          2. Save the GPIF designer project and the generate the .c file using File->Export to GPIF.c file in the GPIF designer.

          3. Add the generated .c file to the Keil project under Source Group.

          4. In the TD_init() call the GPIFInit(); function.

           

          This will initialize the GPIF to the project and eliminate the warning that you see, then you can start using the GPIF registers to configure and operate the interface.

           

          Thanks,

          Yatheesh

          • 2. Re: FX2 streaming and GPIF
            raus_1269711

            Hello,

            Thanks for your reply.

            I had followed the directions given in the document step by step with no avail.

             

            I will do what you suggested.

            My application requires streaming the data. I read Cypress's application notes on streaming and downloaded

            the example program. Although it works, I can not access the data. neither the out nor the in.

            Is there a any modification I can do to the program to resolve this issue?

            Or, are there any sample program that I can use to connect the USB controller to an FPGA.

            My design is very flexible. All I need is the data and the control signals.

             

            Thanks so much

            • 3. Re: FX2 streaming and GPIF
              YatheeshK_36

              Hello,

               

              The streamer application is designed to only test the maximum through put that can be achieved in an application.

               

              You can use the streamer application from the FX3 SDK for windows and display the data that is being streamed using the Show Transferred Data option.

               

               

              We have an Application note where FX2LP configured in Slave FIFO mode is interfaced to FPGA.  Please refer to

              AN61345 - Designing with EZ-USB® FX2LP™ Slave FIFO Interface

              Thanks,

              Yatheesh

              • 4. Re: FX2 streaming and GPIF
                raus_1269711

                Hello Yatheesk,

                 

                Thanks Again,

                 

                My application requires isosynchronous method of transferring data.

                I am evaluating FX2. The problem is The application AN4053 does not provide any real data and controls. The data is generated internally.

                If it is possible please provide how I can modify the firmware to have interface controls with in a real data environment.

                Thanks,

                • 5. Re: FX2 streaming and GPIF
                  YatheeshK_36

                  Hello,

                   

                  Please refer to this Application note: AN63787 which is based on data transfers between 2 FX2LPs.

                  One configured as GPIF master and another configured in Slave FIFO mode.

                   

                  You can use the above application note as a reference when interfacing external peripherals to FX2LP as GPIF master or in Slave FIFO mode.

                   

                  For more details on Slave FIFO implementation refer to AN61345.

                   

                  Thanks,

                  Yatheesh

                  • 6. Re: FX2 streaming and GPIF
                    raus_1269711

                    Thanks, You are very helpful.

                     

                    I have started with a much simpler application given in

                    Interfacing FX2LP™ with Image Sensor – KBA95736

                     

                    I have duplicated  the exact environment, yet it seems, I do not get the data that I provide at port B.

                    According to the application note, the data is 7 bit wide and transferred through port B.

                    Any recommendations?

                     

                    Thanks so much.

                    • 7. Re: FX2 streaming and GPIF
                      YatheeshK_36

                      Hello,

                       

                      Please probe the interface lines to check if the control signals VSYNC and HSYNC are asserted as required.

                       

                      As per the KBA the data bis width is 8-bit wide.

                      D[7:0]: Output data lines that carry the image data.

                      Please interface all the 8-data lines and check if you are receiving the data properly.

                       

                      Thanks,

                      Yatheesh

                      • 8. Re: FX2 streaming and GPIF
                        raus_1269711

                        Hello Yatheesh,

                        I have checked my signals. they appear fine.

                        To get more familiar with  FX2, I designed a simple PCB that uses the 68014, the 56 pin version, and an FPGA from Xilinx,

                        It is very flexible. That is to say, I have connected all of the pins of the USB controller to the FPGA. So I can program any situation.

                        When I program the bulk loop firmware,  everything works fine. I am very sure of it.

                        As soon as I use any of the streaming firmware, I get no data. neither when I write, nor when I read, this is while the streamer C# program indicates that the transfers are successful.

                        No data bits changes, the d lines all  are stuck randomly.

                        I am totally confused.

                        I have searched the internet. It seems that there were other situations such as mine. Unfortunately, I could not find any that got resolved.

                         

                        You have been very responsive. I truly appreciate all your help.

                        Any ideas?

                        Thanks,

                        Ray

                        • 9. Re: FX2 streaming and GPIF
                          YatheeshK_36

                          Hello Ray,

                           

                          Instead of using the streamer application can you please use the control center and do IN transfers on the respective end point and check if you are getting the expected data?

                           

                          Also, please do share your firmware and the Slave FIFO interface signal details so that I can try the same on my side.

                           

                          Thanks,

                          Yatheesh

                          • 10. Re: FX2 streaming and GPIF
                            raus_1269711

                            Hello Yatheesh,

                             

                            Attached is the streaming program. I have downloaded it from application note 4053.

                            I appreciate it greatly if you can let me know what I need to do to get the right data with this program.

                            Externally, my design is very flexible. I can design any situation, flags, or whatever else that is necessary.

                            So far no matter what I have to the firmware, neither the streamer C# program works nor the control center program.

                            All I need is to be able to write and read data as fast as possible. That is to say no other signal processing is going to be assigned to the USB controller.

                            Oh, I can not attach the file, so I email it to you.

                            Thanks,

                            Ray

                            • 11. Re: FX2 streaming and GPIF
                              raus_1269711

                              Hello Yatheesh,

                               

                              In case you dont get my email here is the main program.

                               

                              ////////////////////////

                              #pragma NOIV               // Do not generate interrupt vectors

                              //-----------------------------------------------------------------------------

                              //   File:      CYStream.c

                              //   Contents:   USB Bulk and Isoc streaming example code.

                              //

                              // Copyright (c) 2003, Cypress Semiconductor Corporation All rights reserved

                              //

                              // This software is owned by Cypress Semiconductor Corporation

                              // (Cypress) and is protected by United States copyright laws and

                              // international treaty provisions.  Therefore, unless otherwise specified in a

                              // separate license agreement, you must treat this

                              // software like any other copyrighted material.  Reproduction, modification, translation,

                              // compilation, or representation of this software in any other form

                              // (e.g., paper, magnetic, optical, silicon, etc.) is prohibited

                              // without the express written permission of Cypress.

                              //

                              // Disclaimer: Cypress makes no warranty of any kind, express or implied, with

                              // regard to this material, including, but not limited to, the implied warranties

                              // of merchantability and fitness for a particular purpose. Cypress reserves the

                              // right to make changes without further notice to the materials described

                              // herein. Cypress does not assume any liability arising out of the application

                              // or use of any product or circuit described herein. Cypress’ products described

                              // herein are not authorized for use as components in life-support devices.

                              //

                              // This software is protected by and subject to worldwide patent

                              // coverage, including U.S. and foreign patents. Use may be limited by

                              // and subject to the Cypress Software License Agreement.

                              //

                              //-----------------------------------------------------------------------------

                              #include "fx2.h"

                              #include "fx2regs.h"

                              #include "fx2sdly.h"            // SYNCDELAY macro

                               

                               

                               

                               

                              extern BOOL   GotSUD;         // Received setup data flag

                              extern BOOL   Sleep;

                              extern BOOL   Rwuen;

                              extern BOOL   Selfpwr;

                               

                               

                              #define LED_ADDR 0x21

                               

                               

                              enum {

                                  Alt0_BulkIN = 0,

                                  Alt1_BulkOUT,

                                  Alt2_BulkINOUT,

                                  Alt3_IsocIN,

                                  Alt4_IsocOUT,

                                  Alt5_IsocIN,

                                  Alt6_IsocINOUT

                              };

                               

                               

                              enum {

                                  Full_Alt0_BulkIN = 0,

                                  Full_Alt1_BulkOUT,

                                  Full_Alt2_IsocIN,

                                  Full_Alt3_IsocOUT

                              };

                               

                               

                              BYTE xdata Digit[] = { 0xc0, 0xf9, 0xa4, 0xb0, 0x99, 0x92, 0x82, 0xf8, 0x80, 0x98, 0x88, 0x83, 0xc6, 0xa1, 0x86, 0x8e };

                               

                               

                              BYTE    Configuration;      // Current configuration

                              BYTE    AlternateSetting = Alt0_BulkIN;   // Alternate settings

                               

                               

                               

                               

                              //-----------------------------------------------------------------------------

                              // Task Dispatcher hooks

                              //   The following hooks are called by the task dispatcher.

                              //-----------------------------------------------------------------------------

                               

                               

                              WORD mycount;

                               

                               

                              void TD_Init(void)             // Called once at startup

                              {

                                 int i,j;

                               

                               

                              CPUCS = 0x12; // CLKSPD[1:0]=10, for 48MHz operation

                                                          // CLKOE=1, drive CLKOUT

                                 SYNCDELAY;

                               

                               

                                 // set the slave FIFO interface to 48MHz

                                 IFCONFIG |= 0x40;

                                 SYNCDELAY;

                               

                               

                                  // Default interface uses endpoint 2, zero the valid bit on all others

                                  // Just using endpoint 2, zero the valid bit on all others

                                  EP1OUTCFG = (EP1OUTCFG & 0x7F);

                              SYNCDELAY;

                              EP1INCFG = (EP1INCFG & 0x7F);

                              SYNCDELAY;

                              EP4CFG = (EP4CFG & 0x7F);

                              SYNCDELAY;

                              EP6CFG = (EP6CFG & 0x7F);

                              SYNCDELAY;

                              EP8CFG = (EP8CFG & 0x7F);

                              SYNCDELAY;

                                  EP2CFG = 0xE0;  // EP2 is DIR=IN, TYPE=BULK, SIZE=512, BUF=4x

                               

                               

                                 // We want to get SOF interrupts

                                 USBIE |= bmSOF;

                                

                                 mycount = 0;

                               

                               

                                 // Prepare data

                                 for (i=1;i<5;i++)

                                 {

                                    EP2FIFOBUF[0] = LSB(mycount);

                                    EP2FIFOBUF[1] = MSB(mycount);

                                    EP2FIFOBUF[2] = USBFRAMEL;

                                    EP2FIFOBUF[3] = USBFRAMEH;

                                    EP2FIFOBUF[4] = MICROFRAME;

                                    for (j=5;j<1024;j++)

                                    {

                                       EP2FIFOBUF[j] = i;

                                    }

                                    EP2BCH = 0x02;

                                    EP2BCL = 0x00;

                                 }

                               

                               

                               

                               

                                  Rwuen = TRUE;                 // Enable remote-wakeup

                              }

                               

                               

                              void TD_Poll(void)             // Called repeatedly while the device is idle

                              // ...FX2 in high speed mode

                              if( EZUSB_HIGHSPEED( ) )

                              {

                                  // Perform USB activity based upon the Alt. Interface selected

                                   switch (AlternateSetting)

                                  {

                                      case Alt0_BulkIN:

                                          // Send data on EP2

                                          while(!(EP2468STAT & bmEP2FULL))

                                          {

                                              EP2FIFOBUF[0] = LSB(mycount);

                                              EP2FIFOBUF[1] = MSB(mycount);

                                              EP2FIFOBUF[2] = USBFRAMEL;

                                              EP2FIFOBUF[3] = USBFRAMEH;

                                              EP2FIFOBUF[4] = MICROFRAME;

                               

                                              EP2BCH = 0x02;

                                              EP2BCL = 0x00;

                               

                                              mycount++;

                                          }

                                      break;

                               

                                      case Alt2_BulkINOUT:

                                          // Send data on EP2

                                          while(!(EP2468STAT & bmEP2FULL))

                                          {

                                              EP2FIFOBUF[0] = LSB(mycount);

                                              EP2FIFOBUF[1] = MSB(mycount);

                                              EP2FIFOBUF[2] = USBFRAMEL;

                                              EP2FIFOBUF[3] = USBFRAMEH;

                                              EP2FIFOBUF[4] = MICROFRAME;

                               

                                              EP2BCH = 0x02;

                                              EP2BCL = 0x00;

                               

                                              mycount++;

                                          }

                               

                                          // check EP6 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty

                                          if(!(EP2468STAT & bmEP6EMPTY))

                                          {

                                              EP6BCL = 0x80;          // re(arm) EP6OUT

                                          }

                                      break;

                               

                                      case Alt3_IsocIN:

                                      case Alt5_IsocIN:

                                          // Send data on EP2

                                          while(!(EP2468STAT & bmEP2FULL))

                                          {

                                              EP2FIFOBUF[0] = LSB(mycount);

                                              EP2FIFOBUF[1] = MSB(mycount);

                                              EP2FIFOBUF[2] = USBFRAMEL;

                                              EP2FIFOBUF[3] = USBFRAMEH;

                                              EP2FIFOBUF[4] = MICROFRAME;

                               

                                              EP2BCH = 0x04;

                                              EP2BCL = 0x00;

                               

                                              mycount++;

                                          }

                                      break;

                               

                               

                                      case Alt1_BulkOUT:

                                      case Alt4_IsocOUT:

                                          // check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty

                                          if(!(EP2468STAT & bmEP2EMPTY))

                                          {

                                              EP2BCL = 0x80;          // re(arm) EP2OUT

                                          }

                                      break;

                               

                                      case Alt6_IsocINOUT:

                                      {

                                          // Send data on EP2

                                          while(!(EP2468STAT & bmEP2FULL))

                                          {

                                              EP2FIFOBUF[0] = LSB(mycount);

                                              EP2FIFOBUF[1] = MSB(mycount);

                                              EP2FIFOBUF[2] = USBFRAMEL;

                                              EP2FIFOBUF[3] = USBFRAMEH;

                                              EP2FIFOBUF[4] = MICROFRAME;

                               

                                              EP2BCH = 0x04;

                                              EP2BCL = 0x00;

                               

                                              mycount++;

                                          }

                               

                                          // check EP6 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty

                                          if(!(EP2468STAT & bmEP6EMPTY))

                                          {

                                              EP6BCL = 0x80;          // re(arm) EP6OUT

                                          }

                                      }

                                      break;

                                 }

                                

                              }

                              else // Full Speed

                              {

                                  // Perform USB activity based upon the Alt. Interface selected

                                   switch (AlternateSetting)

                                  {

                                      case Full_Alt0_BulkIN:

                                          // Send data on EP2

                                          while(!(EP2468STAT & bmEP2FULL))

                                          {

                                              EP2FIFOBUF[0] = LSB(mycount);

                                              EP2FIFOBUF[1] = MSB(mycount);

                                              EP2FIFOBUF[2] = USBFRAMEL;

                                              EP2FIFOBUF[3] = USBFRAMEH;

                                              EP2FIFOBUF[4] = MICROFRAME;

                               

                                              EP2BCH = 0x00;

                                              EP2BCL = 0x40;

                               

                                              mycount++;

                                          }

                                      break;

                               

                                      case Full_Alt1_BulkOUT:

                                          // check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty

                                          while(!(EP2468STAT & bmEP2EMPTY))

                                          {

                                              EP2BCL = 0x80;          // re(arm) EP2OUT

                                          }

                                      break;

                               

                                      case Full_Alt2_IsocIN:

                                          // Send data on EP2

                                          while(!(EP2468STAT & bmEP2FULL))

                                          {

                                              EP2FIFOBUF[0] = LSB(mycount);

                                              EP2FIFOBUF[1] = MSB(mycount);

                                              EP2FIFOBUF[2] = USBFRAMEL;

                                              EP2FIFOBUF[3] = USBFRAMEH;

                                              EP2FIFOBUF[4] = MICROFRAME;

                               

                                              EP2BCH = 0x03; // 1023

                                              EP2BCL = 0xFF;

                               

                                              mycount++;

                                          }

                                      break;

                               

                                      case Full_Alt3_IsocOUT:

                                          // check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty

                                          while(!(EP2468STAT & bmEP2EMPTY))

                                          {

                                              EP2BCL = 0x80;          // re(arm) EP2OUT

                                          }

                                      break;

                                 }

                              }

                              }

                               

                               

                               

                               

                               

                               

                              /*

                              BOOL TD_Suspend(void)          // Called before the device goes into suspend mode

                              {

                                 return(TRUE);

                              }

                               

                               

                              BOOL TD_Resume(void)          // Called after the device resumes

                              {

                                 return(TRUE);

                              }

                              */

                               

                               

                              //-----------------------------------------------------------------------------

                              // Device Request hooks

                              //   The following hooks are called by the end point 0 device request parser.

                              //-----------------------------------------------------------------------------

                               

                               

                              BOOL DR_GetDescriptor(void)

                              {

                                 return(TRUE);

                              }

                               

                               

                              BOOL DR_SetConfiguration(void)   // Called when a Set Configuration command is received

                              {

                                 Configuration = SETUPDAT[2];

                                 return(TRUE);            // Handled by user code

                              }

                               

                               

                              BOOL DR_GetConfiguration(void)   // Called when a Get Configuration command is received

                              {

                                 EP0BUF[0] = Configuration;

                                 EP0BCH = 0;

                                 EP0BCL = 1;

                                 return(TRUE);            // Handled by user code

                              }

                               

                               

                              BOOL DR_SetInterface(void)       // Called when a Set Interface command is received

                              {

                                  BYTE updateDisplay = TRUE;

                                  AlternateSetting = SETUPDAT[2];

                               

                               

                              // ...FX2 in high speed mode

                              if( EZUSB_HIGHSPEED( ) )

                              {

                                  // Change configuration based upon the Alt. Interface selected

                                  switch (AlternateSetting)

                                  {

                                      case Alt0_BulkIN:

                                          // Only using endpoint 2, zero the valid bit on all others

                                          // Just using endpoint 2, zero the valid bit on all others

                                          EP2CFG = 0xE0;  // EP2 is DIR=IN, TYPE=BULK, SIZE=512, BUF=4x

                                          SYNCDELAY;

                               

                                          EP1OUTCFG = (EP1OUTCFG & 0x7F);

                                      SYNCDELAY;

                                      EP1INCFG = (EP1INCFG & 0x7F);

                                      SYNCDELAY;

                                      EP4CFG = (EP4CFG & 0x7F);

                                      SYNCDELAY;

                                      EP6CFG = (EP6CFG & 0x7F);

                                      SYNCDELAY;

                                      EP8CFG = (EP8CFG & 0x7F);

                                      SYNCDELAY;

                               

                                          // Clear out any committed packets

                                          FIFORESET = 0x80;

                                          SYNCDELAY;

                                          FIFORESET = 0x02;

                                          SYNCDELAY;

                                          FIFORESET = 0x00;

                                          SYNCDELAY;

                               

                                          // Reset data toggle to 0

                                          TOGCTL = 0x12;  // EP2 IN

                                          TOGCTL = 0x32;  // EP2 IN Reset

                               

                                      break;

                               

                                      case Alt1_BulkOUT:

                                          // Only using endpoint 2, zero the valid bit on all others

                                          EP2CFG = 0xA0;  // EP2 is DIR=OUT, TYPE=BULK, SIZE=512, BUF=4x

                                          SYNCDELAY;

                               

                                          EP1OUTCFG = (EP1OUTCFG & 0x7F);

                                      SYNCDELAY;

                                      EP1INCFG = (EP1INCFG & 0x7F);

                                      SYNCDELAY;

                                      EP4CFG = (EP4CFG & 0x7F);

                                      SYNCDELAY;

                                      EP6CFG = (EP6CFG & 0x7F);

                                      SYNCDELAY;

                                      EP8CFG = (EP8CFG & 0x7F);

                                      SYNCDELAY;

                                        

                                          // OUT endpoints do NOT come up armed

                                          EP2BCL = 0x80; // arm first buffer by writing BC w/skip=1

                                          SYNCDELAY;

                                          EP2BCL = 0x80; // arm second buffer by writing BC w/skip=1

                                          SYNCDELAY;

                                          EP2BCL = 0x80; // arm third buffer by writing BC w/skip=1

                                          SYNCDELAY;

                                          EP2BCL = 0x80; // arm fourth buffer by writing BC w/skip=1

                                         

                                      break;

                               

                                      case Alt2_BulkINOUT:

                                          // Using endpoints 2 & 6, zero the valid bit on all others

                                          EP2CFG = 0xE0; // EP2 is DIR=IN, TYPE=BULK, SIZE=512, BUF=4x

                                      SYNCDELAY;

                                          EP6CFG = 0xA0; // EP6 is DIR=OUT, TYPE=BULK, SIZE=512, BUF=4x  

                                      SYNCDELAY;

                                         

                                          EP1OUTCFG = (EP1OUTCFG & 0x7F);

                                      SYNCDELAY;

                                      EP1INCFG = (EP1INCFG & 0x7F);

                                      SYNCDELAY;

                                      EP4CFG = (EP4CFG & 0x7F);

                                      SYNCDELAY;

                                      EP8CFG = (EP8CFG & 0x7F);

                                      SYNCDELAY;

                               

                                          // Clear out any committed packets

                                          FIFORESET = 0x80;

                                          SYNCDELAY;

                                          FIFORESET = 0x02;

                                          SYNCDELAY;

                                          FIFORESET = 0x00;

                                          SYNCDELAY;

                               

                                          // Reset data toggle to 0

                                          TOGCTL = 0x12;  // EP2 IN

                                          TOGCTL = 0x32;  // EP2 IN Reset

                               

                                          // OUT endpoints do NOT come up armed

                                          EP6BCL = 0x80; // arm first buffer by writing BC w/skip=1

                                          SYNCDELAY;

                                          EP6BCL = 0x80; // arm second buffer by writing BC w/skip=1

                                      SYNCDELAY;

                                      break;

                               

                                      case Alt3_IsocIN:

                                          // Only using endpoint 2, zero the valid bit on all others

                                          EP2CFG = 0xD8;  // EP2 is DIR=IN, TYPE=ISOC, SIZE=1024, BUF=4x

                                          SYNCDELAY;

                                         

                                          EP1OUTCFG = EP1INCFG = EP4CFG = EP6CFG = EP8CFG = 0x00;

                                          SYNCDELAY;

                               

                                          // Clear out any committed packets

                                          FIFORESET = 0x80;

                                          SYNCDELAY;

                                          FIFORESET = 0x02;

                                          SYNCDELAY;

                                          FIFORESET = 0x00;

                                          SYNCDELAY;

                               

                                          // This register sets the number of Isoc packets to send per

                                          // uFrame.  This register is only valid in high speed.

                                          EP2ISOINPKTS = 0x03;

                               

                                      break;

                               

                                      case Alt4_IsocOUT:

                                      {

                                          // Only using endpoint 2, zero the valid bit on all others

                                          EP1OUTCFG = EP1INCFG = EP4CFG = EP6CFG = EP8CFG = 0x00;

                                          SYNCDELAY;

                                          EP2CFG = 0x98;  // EP2 is DIR=OUT, TYPE=ISOC, SIZE=1024, BUF=4x

                                          SYNCDELAY;

                               

                                          // OUT endpoints do NOT come up armed

                                          EP2BCL = 0x80; // arm first buffer by writing BC w/skip=1

                                          SYNCDELAY;

                                          EP2BCL = 0x80; // arm second buffer by writing BC w/skip=1        break;

                               

                                      }

                                      break;

                               

                                      case Alt5_IsocIN:

                                      {

                                          // Only using endpoint 2, zero the valid bit on all others

                                          EP2CFG = 0xD8;  // EP2 is DIR=IN, TYPE=ISOC, SIZE=1024, BUF=4x

                                          SYNCDELAY;

                               

                                          EP1OUTCFG = EP1INCFG = EP4CFG = EP6CFG = EP8CFG = 0x00;

                                          SYNCDELAY;

                               

                                          // Clear out any committed packets

                                          FIFORESET = 0x80;

                                          SYNCDELAY;

                                          FIFORESET = 0x02;

                                          SYNCDELAY;

                                          FIFORESET = 0x00;

                                          SYNCDELAY;

                               

                                          // This register sets the number of Isoc packets to send per

                                          // uFrame.  This register is only valid in high speed.

                                          EP2ISOINPKTS = 0x01;

                                      }

                                      break;

                               

                                      case Alt6_IsocINOUT:

                                      {

                                          // Using endpoints 2 & 6, zero the valid bit on all others

                                          EP2CFG = 0xDA; // EP2 is DIR=IN, TYPE=ISOC, SIZE=1024, BUF=2x

                                          SYNCDELAY;

                                          EP6CFG = 0x9A; // EP6 is DIR=OUT, TYPE=ISOC, SIZE=1024, BUF=2x  

                                          SYNCDELAY;

                               

                                          EP1OUTCFG = EP1INCFG = EP4CFG = EP8CFG = 0x00;

                                          SYNCDELAY;

                               

                                          // Clear out any committed packets

                                          FIFORESET = 0x80;

                                          SYNCDELAY;

                                          FIFORESET = 0x02;

                                          SYNCDELAY;

                                          FIFORESET = 0x00;

                                          SYNCDELAY;

                               

                                          // This register sets the number of Isoc packets to send per

                                          // uFrame.  This register is only valid in high speed.

                                          EP2ISOINPKTS = 0x01;

                               

                                          // OUT endpoints do NOT come up armed

                                          EP6BCL = 0x80; // arm first buffer by writing BC w/skip=1

                                          SYNCDELAY;

                                          EP6BCL = 0x80; // arm second buffer by writing BC w/skip=1

                               

                                      }

                                      break;

                               

                               

                                  }

                              }

                                  else

                                  {

                                  // Change configuration based upon the Alt. Interface selected

                                  switch (AlternateSetting)

                                  {

                                      case Full_Alt0_BulkIN:

                                          // Only using endpoint 2, zero the valid bit on all others

                                          // Just using endpoint 2, zero the valid bit on all others

                                          EP2CFG = 0xE0;  // EP2 is DIR=IN, TYPE=BULK, SIZE=512, BUF=4x

                                          SYNCDELAY;

                               

                                          EP1OUTCFG = (EP1OUTCFG & 0x7F);

                                      SYNCDELAY;

                                      EP1INCFG = (EP1INCFG & 0x7F);

                                      SYNCDELAY;

                                      EP4CFG = (EP4CFG & 0x7F);

                                      SYNCDELAY;

                                      EP6CFG = (EP6CFG & 0x7F);

                                      SYNCDELAY;

                                      EP8CFG = (EP8CFG & 0x7F);

                                      SYNCDELAY;

                               

                                          // Clear out any committed packets

                                          FIFORESET = 0x80;

                                          SYNCDELAY;

                                          FIFORESET = 0x02;

                                          SYNCDELAY;

                                          FIFORESET = 0x00;

                                          SYNCDELAY;

                               

                                          // Reset data toggle to 0

                                          TOGCTL = 0x12;  // EP2 IN

                                          TOGCTL = 0x32;  // EP2 IN Reset

                               

                                      break;

                               

                                      case Full_Alt1_BulkOUT:

                                          // Only using endpoint 2, zero the valid bit on all others

                                          EP2CFG = 0xA0;  // EP2 is DIR=OUT, TYPE=BULK, SIZE=512, BUF=4x

                                          SYNCDELAY;

                               

                                          EP1OUTCFG = (EP1OUTCFG & 0x7F);

                                      SYNCDELAY;

                                      EP1INCFG = (EP1INCFG & 0x7F);

                                      SYNCDELAY;

                                      EP4CFG = (EP4CFG & 0x7F);

                                      SYNCDELAY;

                                      EP6CFG = (EP6CFG & 0x7F);

                                      SYNCDELAY;

                                      EP8CFG = (EP8CFG & 0x7F);

                                      SYNCDELAY;

                                        

                                          // OUT endpoints do NOT come up armed

                                          EP2BCL = 0x80; // arm first buffer by writing BC w/skip=1

                                          SYNCDELAY;

                                          EP2BCL = 0x80; // arm second buffer by writing BC w/skip=1

                                          SYNCDELAY;

                                          EP2BCL = 0x80; // arm third buffer by writing BC w/skip=1

                                          SYNCDELAY;

                                          EP2BCL = 0x80; // arm fourth buffer by writing BC w/skip=1

                                         

                                      break;

                               

                               

                                      case Full_Alt2_IsocIN:

                                          // Only using endpoint 2, zero the valid bit on all others

                                          EP2CFG = 0xD8;  // EP2 is DIR=IN, TYPE=ISOC, SIZE=1024, BUF=4x

                                          SYNCDELAY;

                                         

                                          EP1OUTCFG = EP1INCFG = EP4CFG = EP6CFG = EP8CFG = 0x00;

                                          SYNCDELAY;

                               

                                          // Clear out any committed packets

                                          FIFORESET = 0x80;

                                          SYNCDELAY;

                                          FIFORESET = 0x02;

                                          SYNCDELAY;

                                          FIFORESET = 0x00;

                                          SYNCDELAY;

                               

                                      break;

                               

                                      case Full_Alt3_IsocOUT:

                                      {

                                          // Only using endpoint 2, zero the valid bit on all others

                                          EP1OUTCFG = EP1INCFG = EP4CFG = EP6CFG = EP8CFG = 0x00;

                                          SYNCDELAY;

                                          EP2CFG = 0x98;  // EP2 is DIR=OUT, TYPE=ISOC, SIZE=1024, BUF=4x

                                          SYNCDELAY;

                               

                                          // OUT endpoints do NOT come up armed

                                          EP2BCL = 0x80; // arm first buffer by writing BC w/skip=1

                                          SYNCDELAY;

                                          EP2BCL = 0x80; // arm second buffer by writing BC w/skip=1        break;

                               

                                      }

                                      break;

                               

                                  }

                              }

                               

                               

                                 // Update the display to indicate the currently selected alt. Interface

                              if(updateDisplay)

                              {

                                 //EZUSB_WriteI2C(LED_ADDR, 0x01, &(Digit[AlternateSetting]));

                                 //EZUSB_WaitForEEPROMWrite(LED_ADDR);

                                 updateDisplay = FALSE;

                              }

                               

                               

                                 return(TRUE);            // Handled by user code

                              }

                               

                               

                              BOOL DR_GetInterface(void)       // Called when a Set Interface command is received

                              {

                                 EP0BUF[0] = AlternateSetting;

                                 EP0BCH = 0;

                                 EP0BCL = 1;

                                 return(TRUE);            // Handled by user code

                              }

                               

                               

                              BOOL DR_GetStatus(void)

                              {

                                 return(TRUE);

                              }

                               

                               

                              BOOL DR_ClearFeature(void)

                              {

                                 return(TRUE);

                              }

                               

                               

                              BOOL DR_SetFeature(void)

                              {

                                 return(TRUE);

                              }

                               

                               

                              BOOL DR_VendorCmnd(void)

                              {

                                 return(TRUE);

                              }

                               

                               

                              //-----------------------------------------------------------------------------

                              // USB Interrupt Handlers

                              //   The following functions are called by the USB interrupt jump table.

                              //-----------------------------------------------------------------------------

                               

                               

                              // Setup Data Available Interrupt Handler

                              void ISR_Sudav(void) interrupt 0

                              {

                                 GotSUD = TRUE;            // Set flag

                                 EZUSB_IRQ_CLEAR();

                                 USBIRQ = bmSUDAV;         // Clear SUDAV IRQ

                              }

                               

                               

                              // Setup Token Interrupt Handler

                              void ISR_Sutok(void) interrupt 0

                              {

                                 EZUSB_IRQ_CLEAR();

                                 USBIRQ = bmSUTOK;         // Clear SUTOK IRQ

                              }

                               

                               

                              void ISR_Sof(void) interrupt 0

                              {

                               

                               

                                 EZUSB_IRQ_CLEAR();

                                 USBIRQ = bmSOF;            // Clear SOF IRQ

                              }

                               

                               

                              void ISR_Ures(void) interrupt 0

                              {

                                  // Whenever we get a USB Reset, we should revert to full speed mode

                                  pConfigDscr = pFullSpeedConfigDscr;

                                  ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;

                                  pOtherConfigDscr = pHighSpeedConfigDscr;

                                  ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;

                                

                                 EZUSB_IRQ_CLEAR();

                                 USBIRQ = bmURES;         // Clear URES IRQ

                              }

                               

                               

                              void ISR_Susp(void) interrupt 0

                              {

                                 Sleep = TRUE;

                                 EZUSB_IRQ_CLEAR();

                                 USBIRQ = bmSUSP;

                              }

                               

                               

                              void ISR_Highspeed(void) interrupt 0

                              {

                                 if (EZUSB_HIGHSPEED())

                                 {

                                    pConfigDscr = pHighSpeedConfigDscr;

                                    ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;

                                    pOtherConfigDscr = pFullSpeedConfigDscr;

                                    ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;

                               

                               

                                    // This register sets the number of Isoc packets to send per

                                    // uFrame.  This register is only valid in high speed.

                                    EP2ISOINPKTS = 0x03;

                                 }

                                 else

                                 {

                                    pConfigDscr = pFullSpeedConfigDscr;

                                    pOtherConfigDscr = pHighSpeedConfigDscr;

                                 }

                               

                               

                                 EZUSB_IRQ_CLEAR();

                                 USBIRQ = bmHSGRANT;

                              }

                              void ISR_Ep0ack(void) interrupt 0

                              {

                              }

                              void ISR_Stub(void) interrupt 0

                              {

                              }

                              void ISR_Ep0in(void) interrupt 0

                              {

                              }

                              void ISR_Ep0out(void) interrupt 0

                              {

                              }

                              void ISR_Ep1in(void) interrupt 0

                              {

                              }

                              void ISR_Ep1out(void) interrupt 0

                              {

                              }

                               

                               

                              // ISR_Ep2inout is called on every OUT packet receieved.

                              // We don't do anything with the data.  We just indicate we are done with the buffer.

                              void ISR_Ep2inout(void) interrupt 0

                              {

                                  // Perform USB activity based upon the Alt. Interface selected

                                   switch (AlternateSetting)

                                  {

                                      case Alt1_BulkOUT:

                                      case Alt4_IsocOUT:

                                         // check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty

                                          if(!(EP2468STAT & bmEP2EMPTY))

                                          {

                                              EP2BCL = 0x80;          // re(arm) EP2OUT

                                          }

                                      break;

                               

                               

                                      case Alt2_BulkINOUT:

                                      case Alt6_IsocINOUT:

                                          // check EP6 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty

                                          if(!(EP2468STAT & bmEP6EMPTY))

                                          {

                                              EP6BCL = 0x80;          // re(arm) EP6OUT

                                          }

                                      break;

                                 }

                               

                               

                              }

                              void ISR_Ep4inout(void) interrupt 0

                              {

                              }

                              void ISR_Ep6inout(void) interrupt 0

                              {

                              }

                              void ISR_Ep8inout(void) interrupt 0

                              {

                              }

                              void ISR_Ibn(void) interrupt 0

                              {

                              }

                              void ISR_Ep0pingnak(void) interrupt 0

                              {

                              }

                              void ISR_Ep1pingnak(void) interrupt 0

                              {

                              }

                              void ISR_Ep2pingnak(void) interrupt 0

                              {

                              }

                              void ISR_Ep4pingnak(void) interrupt 0

                              {

                              }

                              void ISR_Ep6pingnak(void) interrupt 0

                              {

                              }

                              void ISR_Ep8pingnak(void) interrupt 0

                              {

                              }

                              void ISR_Errorlimit(void) interrupt 0

                              {

                              }

                              void ISR_Ep2piderror(void) interrupt 0

                              {

                              }

                              void ISR_Ep4piderror(void) interrupt 0

                              {

                              }

                              void ISR_Ep6piderror(void) interrupt 0

                              {

                              }

                              void ISR_Ep8piderror(void) interrupt 0

                              {

                              }

                              void ISR_Ep2pflag(void) interrupt 0

                              {

                              }

                              void ISR_Ep4pflag(void) interrupt 0

                              {

                              }

                              void ISR_Ep6pflag(void) interrupt 0

                              {

                              }

                              void ISR_Ep8pflag(void) interrupt 0

                              {

                              }

                              void ISR_Ep2eflag(void) interrupt 0

                              {

                              }

                              void ISR_Ep4eflag(void) interrupt 0

                              {

                              }

                              void ISR_Ep6eflag(void) interrupt 0

                              {

                              }

                              void ISR_Ep8eflag(void) interrupt 0

                              {

                              }

                              void ISR_Ep2fflag(void) interrupt 0

                              {

                              }

                              void ISR_Ep4fflag(void) interrupt 0

                              {

                              }

                              void ISR_Ep6fflag(void) interrupt 0

                              {

                              }

                              void ISR_Ep8fflag(void) interrupt 0

                              {

                              }

                              void ISR_GpifComplete(void) interrupt 0

                              {

                              }

                              void ISR_GpifWaveform(void) interrupt 0

                              {

                              }

                               

                               

                               

                              ///////////////////////////////////////////////////////////////

                              Thanks,

                              Ray

                              • 12. Re: FX2 streaming and GPIF
                                YatheeshK_36

                                Hello,

                                 

                                You can attach the projects in your responses by choosing the advanced editor and then the insert option.

                                 

                                From the code I can see that the TD_init is used to transfer data through the EP2, this is not recommended to be done as TD_init should only be used to configure the device and initialize variables and EP FIFOs.

                                TD_init will be called only once in the firmware execution. Please refer to the void main() function in the fw.c file of the project.

                                The code that needs to be executed continuously (executable code) should be placed in the  TD_poll which runs after the device is configured as needed in the fw.c file.

                                 

                                I have removed all the cases in your firmware except the ISOC in for alternate interface 5  (length - 1024) and the for loop in the TD_init section.

                                I have added the for loop in to the TD_init section where each time the for loop executes, the data value is incremented after event 1024 bytes/

                                 

                                The data I receive is as below:

                                 

                                 

                                 

                                The firmware works as expected.

                                I have also attached the firmware in this response, please let me know if there are any changes needed.

                                 

                                password for zip: cypress

                                 

                                Thanks,

                                Yatheesh

                                • 13. Re: FX2 streaming and GPIF
                                  raus_1269711

                                  Hello Yatheesh,

                                   

                                  I truly appreciate your quick and professional responses. You are a gem and a great asset to your company.

                                  Just to make sure I test the code under the right circumstances, please let me know what external logic for flags I need.

                                  I can program my FPGA to provide the right signals for read and write.

                                   

                                  Thanks,

                                  Ray

                                   

                                  • 14. Re: FX2 streaming and GPIF
                                    raus_1269711

                                    Hello Yatheesh,

                                    I can duplicate your results,

                                    But the issue is how I can transfer real data in and out of the external FPGA.

                                    I believe with the previous software I was getting the data that was generated by the controller too.

                                     

                                    Thanks,

                                    Ray

                                     

                                     

                                    1 2 Previous Next