7 Replies Latest reply on Aug 1, 2020 1:15 PM by LePo_1062026

    How to implement 4 audio out channels at 96kHz?

    SaMa_4682226

      I’m needing 4 audio out channels at 96kHz, no audio inputs.  I don’t care if it is two I2S ports, or one TDM.

       

      1) Unfortunately, there is only one I2S port.  Is there any way to repurpose the unused I2S input as a second output?

      2) Unfortunately, the max TDM bit rate is too low, even when running at the max clock.

      3) It doesn’t seem that there are enough UDB resources to implement the FIFO in programmable logic.

      4) I can consider alternate parts to PSOC 6.

       

      How might I accomplish this?

       

      Thanks!

        • 1. Re: How to implement 4 audio out channels at 96kHz?
          AashitaR_11

          Hi SaMa_4682226,

           

          CY8CPROTO-062-4343W ( PSoc 6 Wi-Fi BT Prototyping kit ) supports 2 I2S blocks. You can go through the datasheet here- https://www.cypress.com/file/457891/download .

           

          Also, You can find the Knowledge base article (KBA) on importing UDB- based I2S component in a PSoC 6 MCU project in PSoC Creator here- Import UDB-based I2S Component in a PSoC 6 MCU Project (PSoC Creator) – KBA229971 .

          Please go through the above and let us know if you need further clarifications.

           

          Best Regards,

          Aashita

          • 2. Re: How to implement 4 audio out channels at 96kHz?
            SaMa_4682226

            Aashita,

             

            I have that kit and have used that I2S block.

            Unfortunately, it can support only 2 output channels in I2S mode.  TDM mode supports 4 channels, the bit rates are very slow.

             

            If I add a second I2S block, I get these errors:

            Pin guidance unavailable: Resource limit: Maximum number of I2S exceeded (max=1, needed=2).

            Resource limit: Maximum number of I2S exceeded (max=1, needed=2).

             

            How might I get 4 output channels at 96kHz?

             

            Thanks.

            • 3. Re: How to implement 4 audio out channels at 96kHz?
              LePo_1062026

              SaMa,

               

              What is the Cypress device part number you are trying to use?

               

              Aashita mentioned about how to convert a UDB-based I2S implementation from PSoC5 to PSoC6.  However, not all PSoC6s have UDBs.

               

              Also, it was mentioned in the UDB-based I2S datasheet that 96KHz operation was achievable using 64-bit word select period.  This component should be able to support up to 10 channels.

               

              Aashita,

               

              Although the datasheet you referred to indicates on the block diagram (2) I2S, is that 2 separate I2S fixed-function blocks or 1 Rx and 1 Tx I2S fixed-function block?

               

              Len

              • 4. Re: How to implement 4 audio out channels at 96kHz?
                SaMa_4682226

                I’m using CY8CPROTO-062-4343W.  If a PSOC 6 won’t work, I must change parts.

                 

                On the CY8C6247, I can run 2 channel I2S at 96kHz without difficulty.

                 

                The CY8C6247 can have two I2S blocks, but one is TX and the other is RX.  They are fixed function.

                 

                I2S is 2 channel only. Changing to TDM, it supports 8 channels. Channel length is fixed at 32 bit.  With a 50MHz input clock, and a clock divider of 1, the frame rate is a paltry 24kHz.

                 

                If I had a 256 word FIFO, I could maybe reuse the I2S clocks?

                 

                Thanks.

                • 5. Re: How to implement 4 audio out channels at 96kHz?
                  LePo_1062026

                  SaMa,

                   

                  The PSoC6 on the CY8CPROTO-062-4343W has NO UDBs.

                   

                  Many but not all the CY8C6247 series of PSoC6 have UDBs.  

                   

                  As Aashita indicated, it should be possible to import the PSoC5 I2S component to the PSoC6 UDB blocks to give you the additional I2S channels you need and hopefully at the 96KHz rate.

                   

                  Note:  Effectively to use the UDBs and components, you need to use PSoC Creator and not ModusToolbox.

                   

                  Len

                  • 6. Re: How to implement 4 audio out channels at 96kHz?
                    SaMa_4682226

                    Thanks for the note about PSoC Creator vs ModusToolbox.  I was using the wrong approach…

                    It looks like we are getting close.  The UDB based version can support up to 10 channels, each at 96kHz. 

                    It appears that UDB only has a 4 byte fifo.

                    The Modus version has 256 byte fifo.

                     

                    I can’t seem to find the internals of the UDB component to try to extend the fifo.  Where are they located?

                    Resource Meter says I have plenty of resources remaining.

                     

                    Thanks!

                    • 7. Re: How to implement 4 audio out channels at 96kHz?
                      LePo_1062026

                      SaMa,

                       

                      I think there are two approaches you can take to extend the FIFO.

                      1. Find out how the component is handling the FIFO by reverse-engineering the code once the Application is built and modifying the component code.  Probably easier said than done. 
                        Chances are they are using a 4 byte FIFO internal registers that are limited to 4 bytes rather than direct access to RAM.   On the UART, SPI, I2C components to extend beyond the 4 byte default FIFO, there is code to transfer the contents to and from RAM into the FIFO.  The internal FIFO is probably needed to connect to the serial shift register.   It's probably better to use the second approach.
                      2. Create a RAM buffer (maybe a ping-pong type) and DMA to the internal FIFO.  If done properly, this should minimize CPU intervention and still achieve 96KHz data rate.  Additional, it would be a layered augmentation instead of a 'rip-up' of the component code.

                      Len