In our design, the inputs d_in are connected to outputs d_out. Therefore we get a setup time violation of ~22ns.
If we clock sync between output and input like shown in the image
the slack time reduces to ~3ns.
If we double sync with clock, as shown in the image
there is no setup time violation.
Thankyou for your response ... I had actually experimented with this and you are correct it does reduce the problem, however it does this by introducing unnecessary delay and is actually just working around the problem.
The issue as far as I can see it is that the pins are actually NOT connected together ... the input is from the input buffer, and the output is to the pin driver ... the fact that they are related is totally irrelevant to this particular design.
If you use two different sets of pins (with a theoretical external connection) then you have absolutely no issue at all and (without any sync) the paths could all run 120MHz+ (if the device could!)
So whilst I will probably end up using sync to reduce these warnings I don't think it's actually solving the problem. Ideally I need a way to flag that the input and output are unrelated!
Your observations are perfect. The ST Analyzer finds that the inputs are connected to the outputs. On the active clock edge, the inputs really have a setup time violation, since the outputs are changing. Hence, a warning is issued, and the build is completed. We can chose to go ahead with the design as we planned.