5 Replies Latest reply on Jul 28, 2020 2:03 PM by BushraH_91

    s25fl128s advanced verilog model with verbose debug


      The vhdl/verilog model delivered with  s25fl128s are merely basic. I have a large simulation using a preliminary programing sequence followed to reading sequences.

      It is actually painful to debug on waveform every SPI access to decode commands, address and so on.

      I would need a realistic model being able on the top on the functional use to decode commands, address, data received and dump this into log.file

      Do you know if such model exists...

      Any help is welcome.