3 Replies Latest reply on Jul 26, 2020 5:06 AM by LePo_1062026

    CY8C54, QFN 68, Max 2 DAC pins?


      i want to use Voltage DAC with CY8C54, as per the datasheet there is max 2 DAC pins (IDAC/VDAC), and i also read in analog section that any pin can be set as Analog Input or Analog Output, but in the PSoC creator, i have try placing 3 DAC blocks and also selects diff pins in Pin assignment section, why it not showing any error, am i misunderstand something here?


      also please suggest me the dedicated DAC pin if there is any. i want DAC with 0-4V range .








        • 1. Re: CY8C54, QFN 68, Max 2 DAC pins?

          The CY8C54 family does contain only 2DACs. During the build process you will get errors of Resource limit. This limit is not determined when placing the DAC component on the schematic.


          In your screenshot, I am unable to see the completion of the build process. You should get error report as in the following picture:



          You can configure the DAC to provide a full scale voltage of 4.080V. Right click on the DAC component, click configure and then select the Configure tab.


          DAC pins can connect to a pin with the shortest route, and other pins through one or more analog muxes / buses. You can check the pin assigned editor for all the applicable pins the DAC can connect to. DAC[0] can connect to P0[6], and DAC[2] can connect to P0[7]. The two DACs in CY8C54 are named DAC[0] and DAC[2].

          From the workspace explorer, select Design wide resources and then Pins.    



          Best regards,

          Sampath Selvaraj

          • 2. Re: CY8C54, QFN 68, Max 2 DAC pins?

            i am using QFN68 package MCU, could you let me know if i can use any pin as DAC (yes max 2), or fixed pin 55,56?


            • 3. Re: CY8C54, QFN 68, Max 2 DAC pins?



              Although you could use any pin that supports analog, pins 55 and 56 are special in that they are the most directly connected from the DAC resources on the IC to the pins.  In other words, they have the lowest resistance to the pins.


              If you chose to use other other analog pins, the fitter will find the 'best' route through the analog routing fabric.  However each routing switch used to give the signal to the pin will add 100 to 450 ohms.   If you are driving significant current from the DAC (ie 1mA), then you will lose voltage across each routing switch (ie @ 1mA,  450 ohms will drop 0.45V internally).  Additionally, because of the longer and higher resistance routes, the signal will be more prone to internal circuit crosstalk.


              If you want a better 'picture' of what is happening analog-wise, select the "Analog" tab in the Design-Wide Resources (DWR).  On a successfully routed application, you can see the fitter's switch assignments.  The Analog tab is shown here with 2 DACs selected in the TopDesign and routed to pins 55 and 56.



              Hover over a connection point, the tooltip will display the approximate resistance of that routing switch connection.  In the connection to GPIO P0[7] below this is about 250 ohms.

              Next, hover over GPIO P0[7] and right-mouse select, you can select "Start ohm meter" and select "GPIO_P0_7".

              The Ohm Meter appears for the selected net.  Chose the Access point: "DAC0_vout".  It will then display the series resistance between GPIO P0[7] and the DAC0 resource (in this case ~450 ohms).



              In summary, to get the best results, use the recommended pins to output the DAC.   If you prefer to buffer the DAC output through an internal Opamp, the Opamp drive impedance is significantly lower.