9 Replies Latest reply on Aug 7, 2020 5:50 AM by YatheeshK_36

    Slave FIFO Stream IN

    EsPo_3827446

      I referred AN61345 - Designing with EZ-USB® FX2LP™ Slave FIFO Interface and

      I followed Chapter 4.2 Stream IN Transfers and I simulate the FPGA VHDL source code to perform stream IN data transfers.

      the enable signal for the FIFO‟s output driver - SLOE  doesn't change. I shared screenshot for my simulation result.

       

      Data Stream IN State Diagram : flagd == 1 and sync == 1 are Okay.in state diagram SLOE =1 in both state.  why SLOE doesn't change?

      c4.JPG

       

      Thanks

      Esakki

        • 1. Re: Slave FIFO Stream IN
          YatheeshK_36

          Hello Esakki,

           

          When Streaming IN data from FPGA to FX2LP, only the lines SLWR, FLAGD and FADDR comes into play.

          That is, when FPGA starts writing data to FX2LP, SLWR is asserted by FPGA and FPGA starts writing Data to FX2LP till the FLAGD is asserted (pulled low), indicating that the FIFO buffers on the FX2LP is exhausted and FX2LP can take no more data.

           

          SLOE (Slave output enable) is used when FPGA reads data from FX2LP (Slave). Until then the line will not be driven by the FPGA. 

          FPGA read operation is seen in Section 4.3 Stream OUT Transfers of the Application Note .

           

          Please let me know if you have more queries.on AN61345 operation. 

           

          Thanks,

          Yatheesh

          • 2. Re: Slave FIFO Stream IN
            EsPo_3827446

            Hello Yatheesh,

             

            In  my application, I want to send the data from FPGA to FX2LP  and Stream IN only.  Is required to change FX2LP firmware or not?

             

            Thanks

            Esakki

            • 3. Re: Slave FIFO Stream IN
              YatheeshK_36

              Hello Esakki,

               

              There is no need to change the firmware.

              You can use the Streamer Application available in FX2LP DVK or FX3 SDK and use it to stream IN the data from the proper IN END point of FX2LP while the application is running i.e. both the firmware and bitstream is loaded on to FX2LP and FPGA.

               

              Thanks,

              Yatheesh

              • 4. Re: Slave FIFO Stream IN
                EsPo_3827446

                Hello Yatheesh,

                 

                I referred Figure 10. Hardware Connections (Ztex board) in AN61345.

                 

                May I know about PA1, PC0 and PC1 pin in FX2LP connected with FPGA?

                 

                I have few doubts

                [1]  IFCLK   - transfer clock it generated from FPGA to FX2LP pin#20(56-Pin SSOP )  of   in FPGA firmware  is it means "clkout"?

                [2] CLK in fig.10  is it generated from FX2LP   is  PIN # 5 of (56-Pin SSOP  )  conntect with FPGA and  Is it represent clock input for FPGA  "clk"?

                [3] May I know about FX2LP pin for FADDR[1:0]   and  FD[15:0] , pkt_end and done?

                 

                 

                 

                Thanks & Regards

                Esakki

                • 5. Re: Slave FIFO Stream IN
                  YatheeshK_36

                  Hello Esakki,

                   

                  1. PA1 pin:

                  If you are using the ZTEX hardware board, then the FX2LP needs to be programmed first, to set PROG_B pin (which is connected to PA1) of FPGA to HIGH to configure it.

                  The PA1 pin (connected to PROG_B pin of FPGA) is used to enable JTAG configuration of the FPGA so that it can be programmed using JTAG.

                   

                   

                  2. PC0 pin and PC1 pin:

                  Both these pins are use to synchronize between FPGA and FX2LP, when FPGA is being programmed.

                  FX2LP firmware cannot configure the IFCONFIG register to work with external clock before configuring the FPGA to supply the interface clock, So, initially IFCONFIG register is configured to use internal IFCLK (IFCONFIG = 0xE3). 

                   

                  Note that FPGA is not yet configured with the bitstream and the external IFCLK source must be present before the firmware sets IFCONFIG.7 = 0 (IFCLK is provided by external device).

                  To ensure that the FPGA is configured successfully and it can supply IFCLK, the pins PC0 and PC1 are used (check TD_poll).

                   

                  The FX2LP firmware monitors for PC1. FPGA will toggle the PC1 pin (low and then high) to signal FX2LP that it is configured with the bitstream and ready to supply IFCLK. When this happens, the FX2LP will reconfigure to use external clock for the interface (IFCONFIG = 0x03) in the TD_poll.

                  Once the IFCONFIG = 0x03 is successful, FX2LP will signal the FPGA that it is configured to take external IFCLK by signalling high on PC0 and FPGA can now start streaming the data (in or out).

                   

                   

                   

                  [1]  IFCLK   - transfer clock it generated from FPGA to FX2LP pin#20(56-Pin SSOP )  of   in FPGA firmware  is it means "clkout"?

                  ->

                  No, CLKOUT is generated to clock the FPGA using pin #5 (56-Pin SSOP ). CLKOUT is different from IFCLK. IFCLK is used for synchronizing the data transfers between FX2LP and FPGA and is generated by the FGPA once its configured.

                  IFCLK frequency can be varied by the FPGA during data transfers ,whereas, CLKOUT is constant is always provided from the FX2LP to the FPGA.

                   

                   

                  [2] CLK in fig.10  is it generated from FX2LP   is  PIN # 5 of (56-Pin SSOP  )  conntect with FPGA and  Is it represent clock input for FPGA  "clk"?

                  ->

                  Yes, its clock input to FPGA.

                   

                   

                  [3] May I know about FX2LP pin for FADDR[1:0]   and  FD[15:0] , pkt_end and done?

                  ->

                  FIFOADR[1:0] pins is used to select the End point with which the data transfers is done.

                  For example, when FPGA is configured to stream out data to the host through  FX2LP, the respective IN endpoint should be selected using the FIFOADR[1:0] pins.

                   

                  FD[15:0]: Data is transferred though these pins and will be sampled in accordance with the IFCLK signal.

                   

                  pkt_end: when a packet less than the EP size needs to be sent , for example, of only 5 bytes need to be sent from the FPGA, the pkt_end signal can be asserted and the length of the data transferred till the pkt_end signal is asserted will be committed to the USB.

                   

                   

                  Please go through Chapter   9.   Slave FIFOs in the EZ-USB Technical Reference Manual for clear understanding of FX2LP Slave FIFO operation.

                   

                   

                  Thanks,

                  Yatheesh

                  • 6. Re: Slave FIFO Stream IN
                    EsPo_3827446

                    Hello Yatheesh,

                     

                    [1]  I am not using ZTEX hardware board, I am using another FPGA. If PA1 is required  to enable  JTAG configuration, I unable to connect PA1 to Prog_B pin of FPGA because I am using custom board.

                     

                    [2]  May I know PCO an PC1 pin for FPGA configuration. I didn't find FPGA constraint file or connection.

                     

                    [3] Is required to CLK from FX2LP because in my FPGA Clock , an external clock is available. usually I use that clock.

                     

                     

                    I have another question

                     

                    May I know about JTAG configuration for FPGA and Driver?

                     

                    Thanks,

                     

                    Esakki

                    • 7. Re: Slave FIFO Stream IN
                      YatheeshK_36

                      Hello Esakki,

                       

                      1. If your custom board needs the Prog_B signal to be pulled high, then you need to somehow pull the pin high to enable the JTAG on FPGA. Else, the PA1 can be left unconnected.

                       

                      2. The constraints (.ucf) files are present for all the projects in their respective folders.

                       

                      3. If you are using an external clock, then you need not use the CLKOUT from the FX2LP to clock the FPGA.

                       

                       

                      The Section 6.1 ZTEX Hardware Setup in the Application note AN61345 describes the JTAG adapter and the software used.

                       

                      Thanks,

                      Yatheesh

                      • 8. Re: Slave FIFO Stream IN
                        EsPo_3827446

                        Hi Yatheesh,

                         

                        With reference design AN61345 , I want to send 8bit data from fpga instead of 16bit.

                        Is required for any change in FX2LP firmware?

                         

                        Thanks,

                        Esakki

                        • 9. Re: Slave FIFO Stream IN
                          YatheeshK_36

                          Hello Esakki,

                           

                           

                          Yes, there are changes needed in the FX2LP firmware.

                           

                          The Endpoint FIFOs should be configured as 8-bit wide:

                           

                          The bit-0 in EP2FIFOCFG and EP6FIFOCFG should be set to 0 in the firmware:

                           

                          EP2FIFOCFG = 0x11; should be changed to EP2FIFOCFG = 0x10;

                          EP6FIFOCFG = 0x0D;  should be changes to EP6FIFOCFG = 0x0C;

                           

                           

                          Thanks,

                          Yatheesh