3 Replies Latest reply on Jul 28, 2020 5:45 AM by YatheeshK_36

    FX2LP18 - Schematics verifications

    JeBo_4132831

      Hi,

       

      Our FX2LP18 board is quite ready.

       

      I would like to check with you some interrogations.

       

      The VCCIO will be set to 1.8V.

      I2C_SDA/I2C_SCL is pullup with a 1K to 1.8V.

       

      One question, concerning WAKEUP (that we do not want to use) : DO we need to PULLUP it to 1.8V ? or 3.3V ?

       

      We also use a LARGE EEPROM (1.8V). We will connect the A0 to 1.8V through a JUMPER. In this case, we can change the I2C ADRESS to 0xA0 by removinf the JUMPER. In this case, the FX2LP18 will not see the LARGE EEPROM ? Right ?  It can be usefull in case of corrupted EEPROM, to be able to write it again using the CYPRESS VENDOR Comand.

       

      Last question  : What is the difference between IFCLK and CLKOUT if we use the FX2LP18 at the maximun 48MHZ clock ?

       

       

      Regards.

        • 1. Re: FX2LP18 - Schematics verifications
          YatheeshK_36

          Hello,

           

          The I2C lines SCL and SDA should be pulled up to VCCIO with a Resistance of 2.2 K to 10K . In the datasheet, please refer to the pin descriptions of SCL and SDA.

          In the CY3687 DVK a 10K pull up resistance is used on SCL and SDA.

           

          If not used, WAKEUP pin can be pulled up to VCCIO voltage level.

           

           

          On boot-up FX2LP18 checks for EEPROM at both 0x50 and 0x51 (7-bit) slave address and looks for "C2" at the address 0x00 of the EEPROM. So, for the boot to fail you need to electrically disconnect the EEPROM or change the slave address to any other than 0x50 or 0x51 or the first byte of the EEPROM should not contain "0xC2".

           

          Please note that, FX2LP18 does not enumerate using internally stored descriptors (for example, Cypress’s VID/PID/DID is not used for enumeration) when C2 Load fails.

           

          IFCLK is used when interfacing FX2LP18 with an external peripheral using Slave FIFO or GPIF and be used as input or output from FX2LP18.

          IFCLK is necessary for synchronizing the transfers between external peripheral and FX2LP (configured as GPIF or Slave FIFO).

           

          CLKOUT is used to clock an external peripheral continuously if required. For example, on startup, if an FPGA is connected to FX2LP18 and the FPGA needs external clock to configure itself on startup, CLKOUT from FX2LP18 can be used.

          For data transfers in Slave FIFO or GPIF mode IFCLK should be used.

           

          Thanks,

          Yatheesh

          • 2. Re: FX2LP18 - Schematics verifications
            JeBo_4132831

            OK thanks.

             

            Another question related to EEPROM.

            FX2LP18 requires a good EEPROM for 0xC2 Boot Loading.

             

            Then the EEPROM need to be programmed externally (not using the FX2LP18).

            After POWER ON, if EEPROM is not prgrammed, the FX2LP18 bootwill fail and will not be connected to the USB Bus.

            After this, we ant to program the EEPROM using an external tool connected onto SDA/SCL.

            Doing this, Do we need to disconnect physically (using JUMPERS for instance) the SDA/SCL from the FX2LP18.

            Or does the SCL/SDA are internally in TRI-STATE  Mode in the FX2LP18 ?

             

            We imagine put a small firmware in the EEPROM to only connect the USB bus (DISCON and RENUM Bit). After doing this, the FX2LP18 will boot as a Cypress Device Right ? And we then can use the RAM download Vendor Comand from Cypress to downlaod the TRUE firmware (and doing again a RENUMeration to using our VID/PID).

            Is this method correct ?

             

             

            Regards

            • 3. Re: FX2LP18 - Schematics verifications
              YatheeshK_36

              Hello,

               

               

              After this, we want to program the EEPROM using an external tool connected onto SDA/SCL.

              Doing this, Do we need to disconnect physically (using JUMPERS for instance) the SDA/SCL from the FX2LP18.

              Or does the SCL/SDA are internally in TRI-STATE  Mode in the FX2LP18 ?

              The default states of the I2C pins on FX2LP18 is High Z, so the EEPROM need not be disconnected when programming using a different I2C master . Please refer to the pin descriptions in the datasheet.

               

               

              We imagine put a small firmware in the EEPROM to only connect the USB bus (DISCON and RENUM Bit). After doing this, the FX2LP18 will boot as a Cypress Device Right ? And we then can use the RAM download Vendor Comand from Cypress to downlaod the TRUE firmware (and doing again a RENUMeration to using our VID/PID).

              Is this method correct ?

              Yes, this method also can be used to reprogram the EEPROM after the initial firmware from EEPROM is loaded onto FX2LP18 RAM.

               

              Thanks,

              Yatheesh