4 Replies Latest reply on Jul 18, 2020 5:34 PM by SeungM_41

    SD3 (or FX3S) - DDR mode on eMMC interface

    SeungM_41

      Hi

       

      I am writing to you behalf of my customer.
      My customer is using SD3 (CYUSB3025) as eMMC interface on S-port0.
      They have some question about default configuration on S-port0.

      To iitiaize SIB block in cyfx3_msc.c,

          intfParams.resetGpio       = 0xFF;                          /* No GPIO control on SD/MMC power. */
          intfParams.rstActHigh      = CyTrue;                        /* Don't care as no GPIO is selected. */
          intfParams.cardDetType     = CY_U3P_SIB_DETECT_DAT_3;       /* Card detect based on SD_DAT[3]. */
          intfParams.voltageSwGpio   = 45;                            /* Use GPIO_45 for voltage switch on S0 port. */
          intfParams.lvGpioState     = CyFalse;                       /* Driving GPIO low selects 1.8 V on SxVDDQ. */
          intfParams.writeProtEnable = CyFalse;                       /* Write protect handling enabled. */
          intfParams.lowVoltage      = CyTrue;                        /* Low voltage operation enabled. */
          intfParams.useDdr          = CyTrue;                        /* DDR clocking enabled. */
          intfParams.maxFreq         = CY_U3P_SIB_FREQ_104MHZ;        /* No S port clock limitation. */
          intfParams.cardInitDelay   = 0;                             /* No delay required between SD card insertion
                                                                         before initialization. */
      Question#1.
      intfParams.useDdr          = CyTrue;                        /* DDR clocking enabled. */
      as CyTrue for DDR clocking, Does it mean both SDR and DDR can be used? or work as only DDR mode?

       

      Question#2.
      intfParams.maxFreq         = CY_U3P_SIB_FREQ_104MHZ;        /* No S port clock limitation. */
      when they measured clock,  SD3's eMMC clock is 48Mhz. They would like to 52MHz as Max speed of eMMC 4.41. but, Why 48MHz?

      As my personal opinion, they are using 48MHz crystal into SD3 (CYUSB3025). So, SD_clock seems to have 48MHz.
      To use max 52Mhz, SD_clock should be 26Mhz or 52Mhz into SD3 input. Is my understanding correct?
      if there is any method on firmware to increase SD_clock on eMMC interface, please let me know.

       

      Question#3.     
      Can USB Host access directly some register in SD3 (CYUSB3025) (for example, GPIF Configuration Register : 0xE0014000)?
      Can USB Host access (read/write) directly some register in SD3 (CYUSB3025) (for example, GPIF Configuration Register : 0xE0014000)?
      if yes, please let me know how to access the register by USB host.

      GPIF_configuration_Register.png

       

       

      Regards,

      Jake

        • 1. Re: SD3 (or FX3S) - DDR mode on eMMC interface
          JayakrishnaT_76

          Hello Jake,

           

          Please find my comments for your questions below:

          1. If the following setting is used,

          intfParams.useDdr  = CyTrue;

           

          then, only the DDR (52MHz) mode can be used and not both SDR and DDR.

           

          2. The SIB clocks are generated from the System clock by using appropriate dividers. Please refer to Table 3 of SD3 datasheet to understand the supported clock inputs and the configuration of FSLC pins to be used for the same. From section 2.3.1.9 of FX3 TRM, the system clock frequency is 384MHz when the device is clocked with 19.2MHz crystal or 38.4MHz clock input and the system clock frequency is 416MHz when the device is clocked with a 26MHz or 52MHz input clock. If the system clock is 384MHz, then upon the action of the dividers will result an SIB clock of 48MHz only. To obtain a clock of 52MHz, the system clock should be 416MHz. For this, the clock input to SD3 should be either 26MHz or 52MHz.

           

          3. For accessing a particular register inside SD3, a vendor specific SCSI command can be used. Your customer can develop a custom host application that would send a vendor specific SCSI command. For this,the first byte of CBWCB field in the CBW, can be set to 0xC0 to indicate a vendor specific SCSI command. The following byte can be used to indicate the particular SCSI vendor command to be executed.

          Please refer to the following link to understand the different opcodes for SCSI commands:

          https://en.wikipedia.org/wiki/SCSI_command

           

          The command need to be handled in the firmware so that it sends out the required register value through the bulk endpoint.

           

          Best Regards,

          Jayakrishna

          • 2. Re: SD3 (or FX3S) - DDR mode on eMMC interface
            SeungM_41

            Jayakrishna

             

            Thank you so much for your support and kinds of comment.

             

            The command need to be handled in the firmware so that it sends out the required register value through the bulk endpoint.

            ==> Could you please let me know an example code (or location I can download) to handle vendor specific SCSI command in firmware? 

             

             

            Regards,

            Jake

            • 3. Re: SD3 (or FX3S) - DDR mode on eMMC interface
              JayakrishnaT_76

              Hello Jake,

               

              We do not have an example project to share with you at the moment. But you can refer to the SDK example project FX3SMassStorage and handle the vendor specific SCSI command just like other commands. Inside the project, there is a function CyFxMscApplnParseCbw() used for parsing the CBW. Inside this function, there is a switch statement for checking different opcodes. This does not have a case for the vendor specific SCSI command. You can try modifying the switch statement by referring to the following piece of code:

               

              switch (cmd)

               

              {

              ..

              ..

              ..

              case CY_FX_MSC_SCSI_VENDOR: //define this as 0xc0 in .h file

              {

              if(glMscCbwBuffer[CY_FX_SCSI_INQCMD_EVPD_OFFSET] == COMMAND) //define the COMMAND value in .h file

              {

              //retrieve the register value here and call the function CyFxMscApplnSendDataToHost with a pointer to data buffer and length of data

              }

              break;

              }

              default:

              {

              ..

              break;

              }

              }

               

              Please make sure that before calling the function CyFxMscApplnSendDataToHost, glMscState should be CY_FX_MSC_STATE_DATA.

               

              Best Regards,

              Jayakrishna

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              • 4. Re: SD3 (or FX3S) - DDR mode on eMMC interface
                SeungM_41

                Jayakrishna

                 

                Thank you so much for your comment.

                I will try to it and I will update if I have additional question on it.

                 

                Regards,

                Jake