Generally, PSOC5LP I/O pins are limited to around 33Mhz in fast, strong drive mode.
The "Datasheet" button for a pin will show you that.
So, with the CY8CKit-059, you are unable to create a 48Mhz OUTPUT square wave, even with a digital output.
If you wish to do an internal square wave, since the PSOC on that kit is 80mhz, you can make an internal 48mhz square wave and drive some other components, but it will be problematic.
If you can do a special board with a schematic, you can create a 48mhz square wave using discrete components.
Take a look on this example. It outputs almost 80MHz directly on the pin.
The output is not exactly a square wave, but I was able to observe full 5V p-p sine signal using 100 MHz scope. The output is more than just a sine, as multiple harmonics (>200 MHz) can be observed using RTL-SDR radio dongle. Frequency tuning approx 1% using a hyperabrupt varactor and ceramic resonator. Probably some wider tuning can be obtained using external voltage supply for varactor (0-10V), as PSoC Opamps are limited to about +4V.
Can I change the output frequency in this study?
For example now 80Mhz. Can I set this from 1Mhz to 80Mhz?
I haven't tested for continuity of the frequency output, and can't guarantee absence of tuning gaps. The tuning is controlled by varactor capacitance, resonator Q-factor, and PLL parameters P and Q:
Fout = Fxtal x P/Q,
where P is in range [8 to 255], Q is in range [1 to 16]. And Fxtal can be typically adjusted in 1% range by tuning varactor bias voltage.
So PLL could be assigned to quite dense frequency output in 80 to 40MHz. And other frequencies in 1 to 40MHz range can be obtained by
simply dividing that primary output.
Unfortunately, varactor is a non-linear device, so it will be hard to make predictable frequency Fxtal with good repeatability and accuracy.
for wide range tunable frequency output I would recommend external devices, such as
AD9833 or similar DDS module
or Si5351 PLL module
Can I change to p and q with code?
Yes. the P and Q factors can be changed in SW.
I've attached is a C module with APIs to determine the best PLL factors to use. There is a API call uint32 GetBestPLL_BRCfactors(uint32 infreq, uint32 outfreq) you might find useful.
Is this design intended for personal or commercial uses?
When you are generating a square-wave outside the PSoC at such a higher frequency the harmonics are going to be a concern with the FCC and the such. Depending on the power required to drive the signal the harmonics are surely going to be a concern. Although you are probably not desiring to have an "intended radiator" this is what you will most likely have.
In one automotive design, the maximum intended frequency existing my CPU was 20KHz. However due to the design using an internal PLL tuned to 48MHz, the first harmonic (96MHz) was in the FM band and this showed up as audible at the radio station tuned to 96.1MHz.
clks.c.zip 4.0 K
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To set P and Q directly use API:
CY_SET_REG8(&FASTCLK_PLL_Q, PLL_Q ); // Q-divider, PLL_Q value in range [1 to 16]
//The Q divider output Freq (and PFD input Freq) must be between 1-3MHz.
CY_SET_REG8(&FASTCLK_PLL_Q, PLL_P ); // P-divider, PLL_P value in range [8 to 255]
//Valid range is 8 - 255, but this must still give a divided frequency of 1 - 3 MHz (PLLOUT / P); this is the limit of the implementation.
See registers TRM
There are some restrictions on selecting P and Q values
I will try.