1 Reply Latest reply on Jul 14, 2020 5:59 PM by NoriakiT_91

    PSoC 5 I2C slave stuck after address read



      we got a problem with a PSoC 5 CY8C5867 and I2C-Bus.

      Under still unknown circumstances the PSoC stalls the bus by holding the SCL low.

      We need to integrate the PSoC PCB in an older hardware with some issues regarding power supply and I2C bus layout.

      The bus signals are not perfect and do not reach 0V e.g.

      Is the I2C module of the PSoC 5 sensitive to dirty voltages?

      Or what can be the trigger for the I2C stop?

      We use the I2C component 3.50, fixed function, hardware address decode.



        • 1. Re: PSoC 5 I2C slave stuck after address read



          In typical case the SCL line is driven by the master device and the slave device receives the clock signal on the SCL line.

          There is an exceptional case that the slave device drives the SCL line to LOW so-called clock stretching.


          When the master requests a bit of data to the slave device but the slave device is not ready to prepare the data, the slave drives the SCL line to LOW to ask the master device to wait until the data prepared.  If the slave cannot prepare the data, the system will stuck.


          Please refer following I2C bus specification by NXP.



          The possible reason why the PSoC 5LP issues a clock stretching is unknown with current situation.

          It is possible to reset the I2C module or the PSoC 5LP using a timer like a watch dog timer to release the SCL line.