In typical case the SCL line is driven by the master device and the slave device receives the clock signal on the SCL line.
There is an exceptional case that the slave device drives the SCL line to LOW so-called clock stretching.
When the master requests a bit of data to the slave device but the slave device is not ready to prepare the data, the slave drives the SCL line to LOW to ask the master device to wait until the data prepared. If the slave cannot prepare the data, the system will stuck.
Please refer following I2C bus specification by NXP.
The possible reason why the PSoC 5LP issues a clock stretching is unknown with current situation.
It is possible to reset the I2C module or the PSoC 5LP using a timer like a watch dog timer to release the SCL line.