1 Reply Latest reply on Jul 13, 2020 5:03 AM by YatheeshK_36

    Using Two Endpoints In Parallel With Same Data Rate

    FrZa_2625781

      Hi,

       

      I am currently transferring about 4 MB per second with a Slave FIFO design and BULK transfers.

      I use multiple transfers that are pipelined (overlapping) and writing into large buffers, so I get an error free transfer even if Windows is stalling the main software for a few seconds.

      Now I want to transfer an additional data channel with the same device. The data packets received by the Slave FIFO are too large in order to buffer whole packets before then multiplexing them to the FIFO inputs.

      I thought about doubling the FIFO clock and alternating the data onto the FIFO input pins, but then I would have to disentangle/demultiplex the alternating bytes in software which is an unwanted load on the processor.

       

      So I had the idea to do as thought of above, but also alternating the FIFO address, so that I could actually demultiplex the data directly after them entering the chip.

      While the FIFO address setup and hold times are a bit higher than the other ones, they should fit with an 8MHz write frequency.

       

      At the moment I use EP6 with Autoin activated and all I have to do ist setup all the transfers in the queue, submit them, receive the data and resubmit the finished transfers.

      I would switch the FIFO adddress to EP2 for the other data stream, setting up EP2 just the same way that EP6 is setup currently (I have used only half the FIFO buffer memory, so that should be possible).

       

      If I now setup and submit the transfers for EP2 in the same way, could I then get synchronous transfer on both EPs?

       

      Regards,

      Frank