4 Replies Latest reply on Jul 16, 2020 8:35 AM by KyTr_1955226

    CCG3 - Receptacle Pinout for a USB-C (DP Alt Mode E) Monitor?




      I've been working on a USB-C monitor project utilizing a CYPD3120 to handle the USB-C DP and Power Delivery interface.  We are running into some issues getting the device to actually behave as a monitor.  We are able to see the device in windows as a "Generic Non-PnP Monitor", but it cannot be enabled in Display Settings, so I'm thinking something might be fishy with how the DP lanes are wired.


      Our test rig consists of a CCG4 Eval Kit (CY4541) connected in DisplayPort Demo mode as described in Section 6.3 of the CCG4 EVK Guide.  We have tested this with a standard retail USB-C monitor and it works without issue.  This eval kit is connected by USB-C to our test board, which uses a CYPD3120 for the USB-C and a separate Bridge IC (NXP PTN3460I) to convert the (2 DP Lanes + AUX) Displayport to LVDS for output to our display panel as well as provide EDID information to the host PC via the DP AUX lines.


      Our board is acting as a USB-C Monitor, not a dongle, so we are using a USB-C receptacle rather than a USB-C Plug.  I suspect that maybe we have an issue with the pinout of the receptacle in regard to the DP lanes.  We are intending to run the Alt-Mode DP in Mode E.  Here is the schematic of our monitor input connector:



      We know that the CC lines are OK, as the power delivery is working great and we are providing 15V/2.5A to the monitor board with no problems.  One issue we noticed is that SBU1 is assigned to AUX- and SBU2 is assigned to AUX+, which is the reverse of what it should be.  Luckily we were able to account for this in the CYPD3120 firmware by adjusting mux_ctrl_set_cfg() in datamux_ctrl.c to swap the switch positions.


      My main concern is the DP0 and DP1 lanes.  I notice that these are connected to Rx2 and Tx2 respectively.  Is this OK?  Or will we need to switch them to Rx1 and Tx1 for proper function?


      I also have a question regarding the DisplayPort AUX lines.  I found this in mux_ctrl_set_cfg():

                   * Configure AUX1/2 resistor pull up/down based on DP configuration.
                   * If DP Config:
                   * AUX1 : 470K pull down
                   * AUX2 : 4.7M pull down
                   * If Non - DP Config:
                   * AUX1 : 1M pull up
                   * AUX2 : 1M pull down
                  if (dp_sink_get_pin_config () == DP_DFP_D_CONFIG_E)
                      aux_resistor_configure (AUX_1_470K_PD_RESISTOR, AUX_2_4P7MEG_PD_RESISTOR);
                      aux_resistor_configure (AUX_1_1MEG_PU_RESISTOR, AUX_2_1MEG_PD_RESISTOR);


      If I'm not mistaken, shouldn't this be the opposite of the comment?  Going by the VESA standard for DisplayPort, it looks like we want the Sink side to have 1M PU/PD on AUXP and AUXN respectively:


      We actually have these 1M resistors populated external to the CYPD3120, so we have the firmware configured for no internal PU/PD:


      aux_resistor_configure (AUX_NO_RESISTOR, AUX_NO_RESISTOR);


      This seems to work (the AUX+ and AUX- signals look to be within spec) but I wanted to clarify the firmware comments above and make sure I'm understanding correctly.


      Any thoughts are greatly appreciated!




      One more question, would having a USB-C receptacle rather than a plug require use of a Demux such as a TUSB564 on the UFP?  Or would a mux on the DFP be sufficient to put the DP lanes in the correct orientation for the config on the UFP?

        • 1. Re: CCG3 - Receptacle Pinout for a USB-C (DP Alt Mode E) Monitor?



          -Could you please confirm if you are using Display Port mode E? Since you've mentioned that it is a 2-lane DP design and the lines are not routed as per UFP Type-C receptacle assignment.

          -If you flip the cable are you still able to see the monitor come up on the host? Ideally you should have a Alternate Mode capable MUX such as TUSB564 on the sink side as well since its a receptacle design to detect the orientation detection.

          -In the CYPD3120 firmware, the AUX internal resistors are set to 470K and 4.7M to comply with the requirement on Type-C to DP adapter as per the Display port spec.

          -Since the TUSB564 supports SBU switching as well, you could route the AUX lines from the MUX with the external 1M pull up and pull down resistors as you have added on your board.

          -Could you please attach the CC logs to verify if the alternate mode negotiation is completing successfully.


          Best Regards,


          • 2. Re: CCG3 - Receptacle Pinout for a USB-C (DP Alt Mode E) Monitor?



            Thanks for the info.

            It looks like in our next revision of this prototype we will be using a TUSB564.  Right now we are trying to determine if we need a HD3SS460 as well for our design.


            We have tried plugging in the cable in all 4 possible orientations, the monitor shows up in Device Manager as "Generic Non-PnP Monitor" in all orientations, but I am unable to enable the monitor in Display Settings (Selecting "Extend Desktop to this Display" on the dropdown just returns to "Disconnect This Display")


            Just to confirm (since we don't have access to a DisplayPort spec that includes USB-C alt-mode specifications),  the CYPD3120 should be setting 470k and 4.7M internally, and the AUX_N and AUX_P signals will still require their external 1M PD/PU resistors?


            I also have a question regarding the SBU->AUX block of the CCG3.  As per the Architecture TRM, each line has internal PU/PD resistors on the SBU side as well as the AUX side:

            However, in the Registers TRM I can find no reference to the PU/PD resistors on the in (SBU) side before the switches, I can only find control bits for the PU/PD on the output side.  Are they just hidden/preconfigured in some way?  This led to some confusion on our end, thinking that the resistors on the out (AUX) side were for the 1M DisplayPort resistors rather than 470k and 4.7M.  Because the firmware specifically refers to them as AUX resistors, we were under the impression they should be used for 1M.


            I have attached the log of events from the EZ-PD Analyzer upon connection of the USB-C cable.  Looks to me like Alt Mode negotiation begins at around SL#35.


            Thanks again for the info!

            • 3. Re: CCG3 - Receptacle Pinout for a USB-C (DP Alt Mode E) Monitor?



              The logs look fine and it seems that the Display Port negotiation is completing. But it could be possible that it is coming up as Generic Non-PnP Monitor due to hardware connection issue on your test board as you mentioned. Could you please modify the connections as suggested in the first response and let us know if it still comes up in the same way?


              In the CYPD3120 firmware, since it is a Type-C to display port adapter design, the resistors required are 4.7M and 470K as per the Display Port Spec. Since the AUX side resistors are already set internally in the SBU switch, the schematic doesnt include external resistors. If in your design, you route the AUX lines directly from the CCG3 to the bridge IC for your display panel, you can either have external 1M resistors with the firmware configured for no internal resistors or internally configure the resistors and have no external resistors connected.


              As you mentioned, the SBU Ctrl register allows the configuration of the pull up/pull down resistors on the AUX side as required by the Display Port Spec. So, based on the design i.e. either plug/receptacle and source/sink, the resistors can be set to either 1M/1M, 4.7M/470K, 100K/100K.


              Best Regards,


              • 4. Re: CCG3 - Receptacle Pinout for a USB-C (DP Alt Mode E) Monitor?

                So a couple updates:


                We've determined that Mode E isn't actually how we want to operate for this design.

                Since we are only using 2 DP lanes, we have learned we actually want to be operating in Alt-Mode D, which is 2 DP lanes + 2 USB-SS lanes.  We will not actually be using the USB-SS lanes, but Alt-Mode D will allow us to act in a configuration that uses only 2 DisplayPort lanes.  We also learned a helpful tidbit that if the DisplayPort host is expecting 4 DP lanes, even if only two are actually being used (as is our case, we are only supporting 1080p in our application), if all 4 lanes are not present on the sink, DisplayPort link training will fail. 


                This could potentially explain at least part of what we are seeing.  Once we re-spin our PCB for Alt-Mode D as well as integrate a Mux into the design, we should hopefully be OK.