5 Replies Latest reply on Jul 7, 2020 11:43 PM by JayakrishnaT_76

    How to Keep the GPIO50 Pin output status is not change when call CyFxGPIOInit

    xixu_4093676

      In Our application case, We need to change GPIF From 16-bit to 32-bit.

      on 16-bit mode, We can use spi to download FPGA firmware then switch to 32-bit mode and re-configure the GPIO and SPI(call deinit and init module api),

      But the GPIO50 go low when call CyFxGPIOInit,the GPIO50 is connected to PROGRAM_B Pin, it will lead the FPGA lost firmware.

      Any suggestion to let the GPIO50 Pin not change when call CyFxGPIOInit?

        • 1. Re: How to Keep the GPIO50 Pin output status is not change when call CyFxGPIOInit
          JayakrishnaT_76

          Hello,

           

          According to my understanding, you are initially using the IO matrix configuration for 16 bit GPIF data bus width for downloading firmware to FPGA through the SPI interface of FX3. Then you call the function CyFxGPIOInit() to initialize the GPIO block, another function for initializing the SPI block and the SPI data transfer functions for firmware download. After firmware download is done, you are de initializing all the blocks and re-configuring the IO matrix for 32 bit data bus. Again you are initializing the GPIO block using the same function CyFxGPIOInit(). Is my understanding correct?

           

          If my understanding is correct, please let me know the following so that I can analyze your situation better:

          1. What is the state of GPIO50 that is required during downloading firmware to FPGA?

          2. After firmware download is complete, what is the state of GPIO required so that the firmware is not lost in FPGA?

          3. Please share the implementation of the function CyFxGPIOInit() so that I can have a look at it.

           

          Best Regards,

          Jayakrishna

          • 2. Re: How to Keep the GPIO50 Pin output status is not change when call CyFxGPIOInit
            xixu_4093676

            Yes, your understand is correctly.

            GPIO50 is the PROGRAM_B Pin Of FPGA, the pin is used to let FPGA Enter download firmware mode with generate a low pulse .

            we have founds that the IO matrix configuration function "CyU3PDeviceConfigureIOMatrix" will set the GPIO50(PROGRAM_B)  to low level.

            That's not our expected result.

            2. After firmware download is complete, what is the state of GPIO required so that the firmware is not lost in FPGA?

                >> Keep the GPIO50 at High state.

            • 3. Re: How to Keep the GPIO50 Pin output status is not change when call CyFxGPIOInit
              JayakrishnaT_76

              Hello,

               

              Please try pulling up the GPIO50 pin using a 10k resistor. As you are calling CyFxGPIOInit again, we recommend that you configure GPIO50 in such a way that the initial value is HIGH. When you want to program the FPGA, you should drive this pin LOW. Please try this and let us know if it solves your issue.

               

              Best Regards,

              Jayakrishna

              • 4. Re: How to Keep the GPIO50 Pin output status is not change when call CyFxGPIOInit
                xixu_4093676

                Currently, There is  a 10k pull-up registor on GPIO50 Pin.

                For enable program FPGA, a negative pulse need to generate on the GPIO Pin, so after FPGA program done, the Pin states is HIGH.

                As my guess, the function "CyU3PDeviceConfigureIOMatrix" will set the GPIO status to default output low , is it correctly?

                if so, is it possible that provide us one updated sdk library with removing the action on change GPIO50 status?

                • 5. Re: How to Keep the GPIO50 Pin output status is not change when call CyFxGPIOInit
                  JayakrishnaT_76

                  Hello,

                   

                  The function CyU3PDeviceConfigureIOMatrix function will not drive the GPIO LOW.

                   

                  According to your code flow, after downloading the firmware to FPGA, the following are done:

                  1. You de-initialize the GPIO module. This de-initializes and powers off the GPIO block. This makes the GPIOs tristated.

                  2. After this, the function CyU3PDeviceConfigureIOMatrix is called again. This will not change the status of the GPIO.

                  3. After this, the function CyFxGPIOInit will be called. This should be the reason why the GPIO goes LOW.

                   

                  When the function CyFxGPIOInit is called again, the GPIO 50 will be reconfigured. If the outValue for GPIO50 is set as CyFalse, then it will output LOW signal. Please change this parameter to CyTrue so that it will output HIGH when the GPIO is reconfigured. Please let us know if this does not help.

                   

                  Best Regards,

                  Jayakrishna