I will add to this-
It is not clear in the datasheet how to or not to connect the following signals when /BYTE is connected to VSS:
I/O8 to I/O14
Should these signals be grounded? left No-Connect on the PCB?
Also, is the same rule applicable to other Cypress SRAMs? I have read many datasheets from Cypress for TSOP-48 packaged SRAMs and there is no consistent definition for these signals.
Very confusing! thanks for any help....
Please refer following block diagram from the "CY62167G Datasheet Document Number: 001-81537"
The /BYTE input is used to control the input and output buffers only.
On other hands the standby control (POWER DOWN CIRCUIT) is controlled by the CE, /BHE, and /BLE inputs. /BYTE does not affect to the power down mode.
From this block diagram, /BLE should be asserted (driven to LOW) even if the 2Mx8 configuration is used.
For the third row in the truth table the Byte pin need not be high. It can be X (don't care).
When you are using the SRAM as 2M x 8 configuration, the IO 8 - 14, BLE, BHE can be left floating or can be tied GND as per your choice and convenience.
This is applicable to all SRAM parts in our portfolio. I will also provide your feedback to the BU to append the datasheets.
Thank you for the reply, Pradipta.
I guess that by floating /BHE and /BLE, there must be some internal pull down, to ensure that the part doesn't randomly go into low power mode?
I say this because isn't it possible that with floating /BHE and /BLE, these signals are undefined which I thought for CMOS was a bad idea. The gates might end up in the HIGH state, which would trigger low power mode. According to the truth table and the logic diagram, regardless of the other signals on the device, if /BHE and /BLE are both high, then shutdown occurs.
Anyhow thank you for the confirmation that grounding /BHE and /BLE is acceptable, also same for IO8-IO14.