Thank you for uploading your project in Cypress web Forums.
I downloaded your project. The TopDesign of this implementation provided no routing from the UART to the Buf_oe component.
If I understood your intent correctly, below is a TopDesign representation of what you were intending.
In this implementation it takes 7 pins on the PSoC6 to implement with 4 externally routed traces.
Sadly, on a PSoC5 it only takes 1 pin. The rest are internally routed.
Your absolutely correct. There is way to much pin usage, I did not realize that until I finally learned how to synthesize the bufoe component. Same with SmartIO, that was easy to get set up following the provided project but way to much pin usage. Both were disqualified. It appears Cypress has an aversion to one pin half duplex communications...
Second, no matter what I tried, if I connected the UART to the bufoe during synthesize, it would not synthesize.
I ended up running with your design because of that and it offered one pin usage... I called it Len's Half Duplex...
However, no matter what I did... take firmware control of pins and swapping them...
/* Connect SCB2 UART function to pins */ /* Configure pins for UART TX operation */ Cy_GPIO_SetHSIOM(GPIO_PRT10, P10_0_NUM, P6_1_GPIO); Cy_GPIO_SetDrivemode(GPIO_PRT10, P10_0_NUM, CY_GPIO_DM_HIGHZ); Cy_GPIO_SetHSIOM(GPIO_PRT10, P10_1_NUM, P6_1_GPIO); Cy_GPIO_SetDrivemode(GPIO_PRT10, P10_1_NUM, CY_GPIO_DM_STRONG_IN_OFF); /* Configure pins for UART RX operation */ Cy_GPIO_SetHSIOM(GPIO_PRT10, Pin10_1_NUM, P10_0_SCB1_UART_RX); Cy_GPIO_SetDrivemode(GPIO_PRT10, Pin10_1_NUM, CY_GPIO_DM_HIGHZ); /* Configure pins for UART TX operation */ Cy_GPIO_SetHSIOM(GPIO_PRT10, Pin10_1_NUM, P10_1_SCB1_UART_TX); Cy_GPIO_SetDrivemode(GPIO_PRT10, Pin10_1_NUM, CY_GPIO_DM_STRONG_IN_OFF);
Of course the slave would reverse that using Pins 9.0 and 9.1...
I simply could not get it to work with one wire configuration as seen below jumper between 10.1 and 9.1
Of course with two-wire
Worked like a champ...
So, the blue dotted lines on the display means they are NOT actually physically connected... I get that, but I still don't understand if I tell the HSIOM to send the UART_RX to pin 10.1(tx) and on the slave tell HSIOM to send UART_TX to pin 9.0(rx) then why doesn't it do just that? I will have to revisit that... I am @ two weeks behind now so I cant work it now. I am working on sending and receiving files to/from a S3 bucket on AWS IoT Core...
Anyway, the project hardware engineer used some maxim chips to design the one-pin so that I am able to use full duplex UART, however I am going to let them worry about the single pin devices... I was told originally that no hardware mods were going to be made to the devices...
Happy 4th Len!
I meant "if I tell the HSIOM to send the UART_RX to pin 10.1(tx) and on the slave tell HSIOM to send UART_TX to pin 9.1(tx)"