I am using EZI2C Slave Component.
I would like to know how I can get the list of registers that have been read or written to by host since the last call to EZI2C_GetActivity();
Or any other suggested way to get this information. Note that my application requires to know both the read and written to registers to act on them.
I have followed through with the suggestion of reading the EZI2C variables directly in EZI2C_ISR_ExitCallback for
EZI2C_rwOffsetS1; and EZI2C_isr_call_data[lc].index = EZI2C_rwIndexS1;
but I don't get a consistent indication of the read or write.
I have followed some recommendation from the following post PSoC 5LP EZI2C Write but I have not been able to get the read and written to registers identified to act on this.
Any help, specially, if there is code example, that would be very helpfull.
Here is additional info if needed:
I am reading "EZI2C_1_curStatus" directly in the Exit ISR and trying to figure out which registers have been touched (read or written to).
while reg ++ != end
// has any bytes of the register touched?
if ( reg >= EZI2C_1_rwOffsetS1)
if ((reg <= EZI2C_1_rwIndexS1)
if (temp & EZI2C_1_STATUS_READ1)
myregStatus |= EZI2C_1_STATUS_READ1;
if (temp & EZI2C_1_STATUS_WRITE1)
myregStatus |= EZI2C_1_STATUS_WRITE1;
The EZI2C_currStatus has values as but most of the time, I get EZI2C_1_STATUS_WR1BUSY and note EZI2C_1_STATUS_READ1 or EZI2C_1_STATUS_WRITE1
/* Status bit definition */
#define EZI2C_1_STATUS_READ1 (0x01u) /* A read addr 1 operation occurred since last status check */
#define EZI2C_1_STATUS_WRITE1 (0x02u) /* A Write addr 1 operation occurred since last status check */
#define EZI2C_1_STATUS_READ2 (0x04u) /* A read addr 2 operation occurred since last status check */
#define EZI2C_1_STATUS_WRITE2 (0x08u) /* A Write addr 2 operation occurred since last status check */
#define EZI2C_1_STATUS_BUSY (0x10u) /* A start has occurred, but a Stop has not been detected */
#define EZI2C_1_STATUS_RD1BUSY (0x11u) /* Addr 1 read busy */
#define EZI2C_1_STATUS_WR1BUSY (0x12u) /* Addr 1 write busy */
#define EZI2C_1_STATUS_RD2BUSY (0x14u) /* Addr 2 read busy */
#define EZI2C_1_STATUS_WR2BUSY (0x18u) /* Addr 2 write busy */
#define EZI2C_1_STATUS_MASK (0x1Fu) /* Mask for status bits */
#define EZI2C_1_STATUS_ERR (0x80u) /* An Error occurred since last read */