My project designator's hardware engineer told me we are going to communicate with our devices via one-wire, half-duplex, there is only one pin available on the devices and we need to download certifications to them...
I figured I would bit-bang a GPIO pin but now I would like to use the SCB UART to do so, it would keep the clock cycles down according to what I've read...
I was using this Re: Is it possible to connect ports of an UART component to logic gates? note on community to attempt to use the SCB UART and modified it to come up with this design...
I was out on the internet searching how to fix my issues and came across UART Ver 2.5, I thought well I could use that since it supports half-duplex...
LOL LOL LOL well... Of course, it was too simple, that's why I couldn't figure it out! Your right. The master is the only one that can initiate communication.
Thank you very much,
Wait I've been thinking about you answer... I am not sure that it is the correct answer.
You are saying mark the Master as Tx only, that would mean mark the Slave as Rx only.
Then how do they receive and transmit respectively?
I am using a common GPIO pin between them but your solution means that the UART 2.0 component would be able to:
Master: tx and rx on tx pin
Slave: rx and tx on rx pin
I don't think that will work, if so please explain further how you get a UART 2.0 component to rx and tx on the rx pin, and tx and rx on the tx pin. This is why I use the bufoe device and the tx_enable to use the rs485 capability... to disable communication while the Master communicates and I can add a timer so that this is done automatically. When the master transmit, the timer circuit will control the bufoe.
Please further explain your solution.
Just do it software? When you tx and or rx just tell the UART 2.0 component to do it on the same pin. I can do that if that will work. Its brilliant if that's the case, so simple!
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You are correct. I didn't read your initial post correctly. You want Half duplex.
Set up the UART as Full Duplex.
Configure RS-485 Support to be true. This will control the output drive of the Bidirectional pin.
The duplex needs to be handled in SW. When you want to Tx put data in the FIFO, the TX_EN line will be true. When the FIFO is empty and the last bit transferred out, the TX_EN will automatically be inactive allowing data from the slave to be read into the master.