I checked and found that I really used old BSDL file.
My device is CY8C3866LTI-030/DIE.
So by the updated BSDL file CY8C3XXXX_XXX_QFN48_4JTAG.bsdl
the BSR length should be 139.
attribute BOUNDARY_LENGTH of CY8C3XXXX_XXX : entity is 139;
By the PSoC Programmer I received DR: 35.
Could you explain it?
The device is still invisible by JTAG Technologies Provision software.
Looks like I found the problem.
In the customer’s design, line TSRT was connected to XRES pin of the device, not to dedicated TRST for 5-wires JTAG connection.
I paid attention that if run Infra test immediately after “Scan Bus” command in PSoC Programmer, the test passes one time, exclude TRST test.
Using 4-wire or 5-wire BSDL files had not any effect.
The issue is closed.
Sorry, the issue still not closed.
Now, by behavior of Interconnection test I see that only few pins toggled according the BSDL file.
These pins are 30 (P3_1), 31 (P3_2), 36 (P3_6), 37 (P3_7).
Looks like BSR cells order wrong.
Was the BSDL file validated?
Can you please let me know which BSDL file you are referring to here? It is validated, but I can test it again just to confirm.
May be need any Compliance Pattern or a preliminary configuration by SVF?
Do you have any news about the issue?
Sorry, but it is very urgent issue.
Can you please share the schematic of your design? We are looking into the BSDL files, will get back to you as soon as possible.
Please send me your personal e-mail.address